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target/arm: Inline gen_bx_im into callers

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There are only two remaining uses of gen_bx_im.  In each case, we
know the destination mode -- not changing in the case of gen_jmp
or changing in the case of trans_BLX_i.  Use this to simplify the
surrounding code.

For trans_BLX_i, use gen_jmp for the actual branch.  For gen_jmp,
use gen_set_pc_im to set up the single-step.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-70-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:59 -07:00 committed by Peter Maydell
parent 0831403b08
commit eac2f39602
1 changed files with 7 additions and 19 deletions
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26
target/arm/translate.c
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@ -765,21 +765,6 @@ static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
tcg_gen_movi_i32(cpu_R[15], val); tcg_gen_movi_i32(cpu_R[15], val);
} }
/* Set PC and Thumb state from an immediate address. */
static inline void gen_bx_im(DisasContext *s, uint32_t addr)
{
TCGv_i32 tmp;
s->base.is_jmp = DISAS_JUMP;
if (s->thumb != (addr & 1)) {
tmp = tcg_temp_new_i32();
tcg_gen_movi_i32(tmp, addr & 1);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb));
tcg_temp_free_i32(tmp);
}
tcg_gen_movi_i32(cpu_R[15], addr & ~1);
}
/* Set PC and Thumb state from var. var is marked as dead. */ /* Set PC and Thumb state from var. var is marked as dead. */
static inline void gen_bx(DisasContext *s, TCGv_i32 var) static inline void gen_bx(DisasContext *s, TCGv_i32 var)
{ {
@ -2725,9 +2710,8 @@ static inline void gen_jmp (DisasContext *s, uint32_t dest)
{ {
if (unlikely(is_singlestepping(s))) { if (unlikely(is_singlestepping(s))) {
/* An indirect jump so that we still trigger the debug exception. */ /* An indirect jump so that we still trigger the debug exception. */
if (s->thumb) gen_set_pc_im(s, dest);
dest |= 1; s->base.is_jmp = DISAS_JUMP;
gen_bx_im(s, dest);
} else { } else {
gen_goto_tb(s, 0, dest); gen_goto_tb(s, 0, dest);
} }
@ -10138,12 +10122,16 @@ static bool trans_BL(DisasContext *s, arg_i *a)
static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
{ {
TCGv_i32 tmp;
/* For A32, ARCH(5) is checked near the start of the uncond block. */ /* For A32, ARCH(5) is checked near the start of the uncond block. */
if (s->thumb && (a->imm & 2)) { if (s->thumb && (a->imm & 2)) {
return false; return false;
} }
tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb); tmp = tcg_const_i32(!s->thumb);
store_cpu_field(tmp, thumb);
gen_jmp(s, (read_pc(s) & ~3) + a->imm);
return true; return true;
} }