hw/misc/edu: support MSI interrupt
So now edu device can support both line or msi interrupt, depending on how user configures it. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <1475067819-21413-1-git-send-email-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -52,7 +52,7 @@ size == 8 for the rest.
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0x20 (RW) : status register, bitwise OR
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0x20 (RW) : status register, bitwise OR
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0x01 -- computing factorial (RO)
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0x01 -- computing factorial (RO)
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0x80 -- raise interrupt 0x01 after finishing factorial computation
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0x80 -- raise interrupt after finishing factorial computation
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0x24 (RO) : interrupt status register
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0x24 (RO) : interrupt status register
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It contains values which raised the interrupt (see interrupt raise
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It contains values which raised the interrupt (see interrupt raise
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@ -87,6 +87,11 @@ An IRQ is generated when written to the interrupt raise register. The value
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appears in interrupt status register when the interrupt is raised and has to
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appears in interrupt status register when the interrupt is raised and has to
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be written to the interrupt acknowledge register to lower it.
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be written to the interrupt acknowledge register to lower it.
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The device supports both INTx and MSI interrupt. By default, INTx is
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used. Even if the driver disabled INTx and only uses MSI, it still
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needs to update the acknowledge register at the end of the IRQ handler
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routine.
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DMA controller
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DMA controller
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--------------
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--------------
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One has to specify, source, destination, size, and start the transfer. One
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One has to specify, source, destination, size, and start the transfer. One
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@ -24,6 +24,7 @@
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/msi.h"
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#include "qemu/timer.h"
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#include "qemu/timer.h"
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#include "qemu/main-loop.h" /* iothread mutex */
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#include "qemu/main-loop.h" /* iothread mutex */
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#include "qapi/visitor.h"
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#include "qapi/visitor.h"
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@ -69,11 +70,20 @@ typedef struct {
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uint64_t dma_mask;
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uint64_t dma_mask;
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} EduState;
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} EduState;
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static bool edu_msi_enabled(EduState *edu)
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{
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return msi_enabled(&edu->pdev);
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}
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static void edu_raise_irq(EduState *edu, uint32_t val)
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static void edu_raise_irq(EduState *edu, uint32_t val)
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{
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{
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edu->irq_status |= val;
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edu->irq_status |= val;
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if (edu->irq_status) {
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if (edu->irq_status) {
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pci_set_irq(&edu->pdev, 1);
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if (edu_msi_enabled(edu)) {
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msi_notify(&edu->pdev, 0);
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} else {
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pci_set_irq(&edu->pdev, 1);
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}
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}
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}
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}
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}
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@ -81,7 +91,7 @@ static void edu_lower_irq(EduState *edu, uint32_t val)
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{
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{
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edu->irq_status &= ~val;
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edu->irq_status &= ~val;
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if (!edu->irq_status) {
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if (!edu->irq_status && !edu_msi_enabled(edu)) {
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pci_set_irq(&edu->pdev, 0);
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pci_set_irq(&edu->pdev, 0);
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}
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}
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}
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}
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@ -342,6 +352,10 @@ static void pci_edu_realize(PCIDevice *pdev, Error **errp)
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pci_config_set_interrupt_pin(pci_conf, 1);
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pci_config_set_interrupt_pin(pci_conf, 1);
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if (msi_init(pdev, 0, 1, true, false, errp)) {
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return;
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}
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memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
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memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
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"edu-mmio", 1 << 20);
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"edu-mmio", 1 << 20);
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pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
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pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
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