acpi, acpi_piix, vt82c686: factor out PM1_CNT logic
factor out ACPI PM1_CNT logic. This will be used by ich9 acpi. Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Huacai Chen <zltjiangshi@gmail.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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04dc308f68
commit
eaba51c573
49
hw/acpi.c
49
hw/acpi.c
@ -279,3 +279,52 @@ void acpi_pm_tmr_reset(ACPIPMTimer *tmr)
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tmr->overflow_time = 0;
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qemu_del_timer(tmr->timer);
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}
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/* ACPI PM1aCNT */
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void acpi_pm1_cnt_init(ACPIPM1CNT *pm1_cnt, qemu_irq cmos_s3)
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{
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pm1_cnt->cmos_s3 = cmos_s3;
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}
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void acpi_pm1_cnt_write(ACPIPM1EVT *pm1a, ACPIPM1CNT *pm1_cnt, uint16_t val)
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{
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pm1_cnt->cnt = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
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if (val & ACPI_BITMASK_SLEEP_ENABLE) {
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/* change suspend type */
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uint16_t sus_typ = (val >> 10) & 7;
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switch(sus_typ) {
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case 0: /* soft power off */
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qemu_system_shutdown_request();
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break;
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case 1:
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/* ACPI_BITMASK_WAKE_STATUS should be set on resume.
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Pretend that resume was caused by power button */
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pm1a->sts |=
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(ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_POWER_BUTTON_STATUS);
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qemu_system_reset_request();
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qemu_irq_raise(pm1_cnt->cmos_s3);
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default:
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break;
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}
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}
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}
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void acpi_pm1_cnt_update(ACPIPM1CNT *pm1_cnt,
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bool sci_enable, bool sci_disable)
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{
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/* ACPI specs 3.0, 4.7.2.5 */
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if (sci_enable) {
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pm1_cnt->cnt |= ACPI_BITMASK_SCI_ENABLE;
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} else if (sci_disable) {
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pm1_cnt->cnt &= ~ACPI_BITMASK_SCI_ENABLE;
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}
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}
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void acpi_pm1_cnt_reset(ACPIPM1CNT *pm1_cnt)
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{
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pm1_cnt->cnt = 0;
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if (pm1_cnt->cmos_s3) {
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qemu_irq_lower(pm1_cnt->cmos_s3);
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}
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}
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14
hw/acpi.h
14
hw/acpi.h
@ -112,4 +112,18 @@ void acpi_pm1_evt_write_sts(ACPIPM1EVT *pm1, ACPIPMTimer *tmr, uint16_t val);
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void acpi_pm1_evt_power_down(ACPIPM1EVT *pm1, ACPIPMTimer *tmr);
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void acpi_pm1_evt_reset(ACPIPM1EVT *pm1);
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/* PM1a_CNT: piix and ich9 don't implement PM1b CNT. */
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struct ACPIPM1CNT {
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uint16_t cnt;
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qemu_irq cmos_s3;
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};
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typedef struct ACPIPM1CNT ACPIPM1CNT;
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void acpi_pm1_cnt_init(ACPIPM1CNT *pm1_cnt, qemu_irq cmos_s3);
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void acpi_pm1_cnt_write(ACPIPM1EVT *pm1a, ACPIPM1CNT *pm1_cnt, uint16_t val);
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void acpi_pm1_cnt_update(ACPIPM1CNT *pm1_cnt,
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bool sci_enable, bool sci_disable);
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void acpi_pm1_cnt_reset(ACPIPM1CNT *pm1_cnt);
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#endif /* !QEMU_HW_ACPI_H */
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@ -55,7 +55,7 @@ typedef struct PIIX4PMState {
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PCIDevice dev;
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IORange ioport;
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ACPIPM1EVT pm1a;
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uint16_t pmcntrl;
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ACPIPM1CNT pm1_cnt;
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APMState apm;
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@ -65,7 +65,6 @@ typedef struct PIIX4PMState {
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uint32_t smb_io_base;
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qemu_irq irq;
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qemu_irq cmos_s3;
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qemu_irq smi_irq;
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int kvm_enabled;
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@ -124,30 +123,7 @@ static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
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pm_update_sci(s);
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break;
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case 0x04:
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{
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int sus_typ;
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s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
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if (val & ACPI_BITMASK_SLEEP_ENABLE) {
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/* change suspend type */
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sus_typ = (val >> 10) & 7;
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switch(sus_typ) {
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case 0: /* soft power off */
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qemu_system_shutdown_request();
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break;
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case 1:
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/* ACPI_BITMASK_WAKE_STATUS should be set on resume.
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Pretend that resume was caused by power button */
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s->pm1a.sts |= (ACPI_BITMASK_WAKE_STATUS |
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ACPI_BITMASK_POWER_BUTTON_STATUS);
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qemu_system_reset_request();
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if (s->cmos_s3) {
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qemu_irq_raise(s->cmos_s3);
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}
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default:
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break;
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}
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}
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}
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acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
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break;
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default:
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break;
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@ -170,7 +146,7 @@ static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
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val = s->pm1a.en;
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break;
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case 0x04:
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val = s->pmcntrl;
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val = s->pm1_cnt.cnt;
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break;
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case 0x08:
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val = acpi_pm_tmr_get(&s->tmr);
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@ -193,11 +169,7 @@ static void apm_ctrl_changed(uint32_t val, void *arg)
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PIIX4PMState *s = arg;
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/* ACPI specs 3.0, 4.7.2.5 */
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if (val == ACPI_ENABLE) {
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s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
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} else if (val == ACPI_DISABLE) {
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s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
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}
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acpi_pm1_cnt_update(&s->pm1_cnt, val == ACPI_ENABLE, val == ACPI_DISABLE);
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if (s->dev.config[0x5b] & (1 << 1)) {
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if (s->smi_irq) {
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@ -276,7 +248,7 @@ static const VMStateDescription vmstate_acpi = {
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VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
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VMSTATE_UINT16(pm1a.sts, PIIX4PMState),
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VMSTATE_UINT16(pm1a.en, PIIX4PMState),
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VMSTATE_UINT16(pmcntrl, PIIX4PMState),
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VMSTATE_UINT16(pm1_cnt.cnt, PIIX4PMState),
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VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(tmr.timer, PIIX4PMState),
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VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
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@ -396,7 +368,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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s = DO_UPCAST(PIIX4PMState, dev, dev);
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s->irq = sci_irq;
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s->cmos_s3 = cmos_s3;
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acpi_pm1_cnt_init(&s->pm1_cnt, cmos_s3);
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s->smi_irq = smi_irq;
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s->kvm_enabled = kvm_enabled;
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@ -157,7 +157,7 @@ static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
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typedef struct VT686PMState {
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PCIDevice dev;
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ACPIPM1EVT pm1a;
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uint16_t pmcntrl;
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ACPIPM1CNT pm1_cnt;
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APMState apm;
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ACPIPMTimer tmr;
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PMSMBus smb;
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@ -209,21 +209,7 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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pm_update_sci(s);
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break;
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case 0x04:
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{
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int sus_typ;
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s->pmcntrl = val & ~(SUS_EN);
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if (val & SUS_EN) {
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/* change suspend type */
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sus_typ = (val >> 10) & 3;
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switch (sus_typ) {
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case 0: /* soft power off */
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qemu_system_shutdown_request();
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break;
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default:
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break;
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}
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}
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}
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acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
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break;
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default:
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break;
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@ -245,7 +231,7 @@ static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
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val = s->pm1a.en;
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break;
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case 0x04:
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val = s->pmcntrl;
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val = s->pm1_cnt.cnt;
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break;
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default:
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val = 0;
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@ -322,7 +308,7 @@ static const VMStateDescription vmstate_acpi = {
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VMSTATE_PCI_DEVICE(dev, VT686PMState),
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VMSTATE_UINT16(pm1a.sts, VT686PMState),
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VMSTATE_UINT16(pm1a.en, VT686PMState),
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VMSTATE_UINT16(pmcntrl, VT686PMState),
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VMSTATE_UINT16(pm1_cnt.cnt, VT686PMState),
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VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(tmr.timer, VT686PMState),
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VMSTATE_INT64(tmr.overflow_time, VT686PMState),
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@ -446,6 +432,7 @@ static int vt82c686b_pm_initfn(PCIDevice *dev)
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apm_init(&s->apm, NULL, s);
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acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
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acpi_pm1_cnt_init(&s->pm1_cnt, NULL);
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pm_smbus_init(&s->dev.qdev, &s->smb);
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