target-alpha: Add various symbolic constants.
The EXC_M_* constants were being set for the EV6, not as set for the Unix kernel entry point. Use PS_USER_MODE instead of hard-coding access to the PS register. Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -274,11 +274,6 @@ struct CPUAlphaState {
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#define cpu_gen_code cpu_alpha_gen_code
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#define cpu_signal_handler cpu_alpha_signal_handler
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static inline int cpu_mmu_index (CPUState *env)
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{
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return (env->ps >> 3) & 1;
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}
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#include "cpu-all.h"
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enum {
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@ -305,14 +300,49 @@ enum {
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EXCP_STQ_C,
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};
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/* Arithmetic exception */
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#define EXC_M_IOV (1<<16) /* Integer Overflow */
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#define EXC_M_INE (1<<15) /* Inexact result */
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#define EXC_M_UNF (1<<14) /* Underflow */
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#define EXC_M_FOV (1<<13) /* Overflow */
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#define EXC_M_DZE (1<<12) /* Division by zero */
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#define EXC_M_INV (1<<11) /* Invalid operation */
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#define EXC_M_SWC (1<<10) /* Software completion */
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/* Hardware interrupt (entInt) constants. */
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enum {
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INT_K_IP,
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INT_K_CLK,
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INT_K_MCHK,
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INT_K_DEV,
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INT_K_PERF,
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};
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/* Memory management (entMM) constants. */
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enum {
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MM_K_TNV,
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MM_K_ACV,
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MM_K_FOR,
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MM_K_FOE,
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MM_K_FOW
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};
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/* Arithmetic exception (entArith) constants. */
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enum {
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EXC_M_SWC = 1, /* Software completion */
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EXC_M_INV = 2, /* Invalid operation */
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EXC_M_DZE = 4, /* Division by zero */
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EXC_M_FOV = 8, /* Overflow */
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EXC_M_UNF = 16, /* Underflow */
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EXC_M_INE = 32, /* Inexact result */
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EXC_M_IOV = 64 /* Integer Overflow */
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};
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/* Processor status constants. */
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enum {
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/* Low 3 bits are interrupt mask level. */
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PS_INT_MASK = 7,
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/* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
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The Unix PALcode only uses bit 4. */
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PS_USER_MODE = 8
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};
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static inline int cpu_mmu_index(CPUState *env)
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{
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return (env->ps & PS_USER_MODE) != 0;
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}
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enum {
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IR_V0 = 0,
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@ -3269,7 +3269,7 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model)
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env->amask = amask;
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#if defined (CONFIG_USER_ONLY)
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env->ps = 1 << 3;
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env->ps = PS_USER_MODE;
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cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD
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| FPCR_UNFD | FPCR_INED | FPCR_DNOD));
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#endif
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