hvf: arm: Raise an exception for sysreg by default
Any sysreg access results in an exception unless defined otherwise so we should raise an exception by default. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Akihiko Odaki
Peter Maydell
parent
0d2aac4ab1
commit
e9e640148c
@ -1199,57 +1199,56 @@ static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val)
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return false;
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}
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static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
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static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val)
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{
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ARMCPU *arm_cpu = ARM_CPU(cpu);
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CPUARMState *env = &arm_cpu->env;
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uint64_t val = 0;
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switch (reg) {
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case SYSREG_CNTPCT_EL0:
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val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
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*val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
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gt_cntfrq_period_ns(arm_cpu);
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break;
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return 0;
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case SYSREG_PMCR_EL0:
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val = env->cp15.c9_pmcr;
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break;
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*val = env->cp15.c9_pmcr;
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return 0;
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case SYSREG_PMCCNTR_EL0:
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pmu_op_start(env);
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val = env->cp15.c15_ccnt;
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*val = env->cp15.c15_ccnt;
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pmu_op_finish(env);
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break;
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return 0;
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case SYSREG_PMCNTENCLR_EL0:
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val = env->cp15.c9_pmcnten;
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break;
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*val = env->cp15.c9_pmcnten;
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return 0;
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case SYSREG_PMOVSCLR_EL0:
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val = env->cp15.c9_pmovsr;
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break;
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*val = env->cp15.c9_pmovsr;
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return 0;
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case SYSREG_PMSELR_EL0:
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val = env->cp15.c9_pmselr;
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break;
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*val = env->cp15.c9_pmselr;
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return 0;
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case SYSREG_PMINTENCLR_EL1:
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val = env->cp15.c9_pminten;
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break;
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*val = env->cp15.c9_pminten;
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return 0;
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case SYSREG_PMCCFILTR_EL0:
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val = env->cp15.pmccfiltr_el0;
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break;
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*val = env->cp15.pmccfiltr_el0;
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return 0;
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case SYSREG_PMCNTENSET_EL0:
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val = env->cp15.c9_pmcnten;
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break;
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*val = env->cp15.c9_pmcnten;
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return 0;
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case SYSREG_PMUSERENR_EL0:
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val = env->cp15.c9_pmuserenr;
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break;
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*val = env->cp15.c9_pmuserenr;
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return 0;
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case SYSREG_PMCEID0_EL0:
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case SYSREG_PMCEID1_EL0:
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/* We can't really count anything yet, declare all events invalid */
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val = 0;
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break;
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*val = 0;
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return 0;
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case SYSREG_OSLSR_EL1:
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val = env->cp15.oslsr_el1;
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break;
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*val = env->cp15.oslsr_el1;
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return 0;
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case SYSREG_OSDLR_EL1:
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/* Dummy register */
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break;
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return 0;
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case SYSREG_ICC_AP0R0_EL1:
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case SYSREG_ICC_AP0R1_EL1:
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case SYSREG_ICC_AP0R2_EL1:
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@ -1276,9 +1275,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
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case SYSREG_ICC_SRE_EL1:
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case SYSREG_ICC_CTLR_EL1:
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/* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
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if (!hvf_sysreg_read_cp(cpu, reg, &val)) {
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hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
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return 1;
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if (hvf_sysreg_read_cp(cpu, reg, &val)) {
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return 0;
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}
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break;
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case SYSREG_DBGBVR0_EL1:
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@ -1297,8 +1295,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
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case SYSREG_DBGBVR13_EL1:
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case SYSREG_DBGBVR14_EL1:
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case SYSREG_DBGBVR15_EL1:
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val = env->cp15.dbgbvr[SYSREG_CRM(reg)];
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break;
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*val = env->cp15.dbgbvr[SYSREG_CRM(reg)];
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return 0;
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case SYSREG_DBGBCR0_EL1:
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case SYSREG_DBGBCR1_EL1:
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case SYSREG_DBGBCR2_EL1:
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@ -1315,8 +1313,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
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case SYSREG_DBGBCR13_EL1:
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case SYSREG_DBGBCR14_EL1:
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case SYSREG_DBGBCR15_EL1:
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val = env->cp15.dbgbcr[SYSREG_CRM(reg)];
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break;
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*val = env->cp15.dbgbcr[SYSREG_CRM(reg)];
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return 0;
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case SYSREG_DBGWVR0_EL1:
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case SYSREG_DBGWVR1_EL1:
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case SYSREG_DBGWVR2_EL1:
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@ -1333,8 +1331,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
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case SYSREG_DBGWVR13_EL1:
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case SYSREG_DBGWVR14_EL1:
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case SYSREG_DBGWVR15_EL1:
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val = env->cp15.dbgwvr[SYSREG_CRM(reg)];
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break;
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*val = env->cp15.dbgwvr[SYSREG_CRM(reg)];
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return 0;
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case SYSREG_DBGWCR0_EL1:
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case SYSREG_DBGWCR1_EL1:
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case SYSREG_DBGWCR2_EL1:
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@ -1351,35 +1349,25 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
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case SYSREG_DBGWCR13_EL1:
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case SYSREG_DBGWCR14_EL1:
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case SYSREG_DBGWCR15_EL1:
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val = env->cp15.dbgwcr[SYSREG_CRM(reg)];
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break;
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*val = env->cp15.dbgwcr[SYSREG_CRM(reg)];
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return 0;
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default:
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if (is_id_sysreg(reg)) {
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/* ID system registers read as RES0 */
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val = 0;
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break;
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*val = 0;
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return 0;
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}
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cpu_synchronize_state(cpu);
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trace_hvf_unhandled_sysreg_read(env->pc, reg,
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SYSREG_OP0(reg),
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SYSREG_OP1(reg),
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SYSREG_CRN(reg),
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SYSREG_CRM(reg),
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SYSREG_OP2(reg));
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hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
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return 1;
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}
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trace_hvf_sysreg_read(reg,
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SYSREG_OP0(reg),
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SYSREG_OP1(reg),
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SYSREG_CRN(reg),
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SYSREG_CRM(reg),
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SYSREG_OP2(reg),
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val);
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hvf_set_reg(cpu, rt, val);
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return 0;
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cpu_synchronize_state(cpu);
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trace_hvf_unhandled_sysreg_read(env->pc, reg,
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SYSREG_OP0(reg),
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SYSREG_OP1(reg),
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SYSREG_CRN(reg),
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SYSREG_CRM(reg),
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SYSREG_OP2(reg));
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hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
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return 1;
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}
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static void pmu_update_irq(CPUARMState *env)
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@ -1503,7 +1491,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
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pmu_op_start(env);
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env->cp15.c15_ccnt = val;
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pmu_op_finish(env);
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break;
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return 0;
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case SYSREG_PMCR_EL0:
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pmu_op_start(env);
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@ -1523,45 +1511,45 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
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env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK);
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pmu_op_finish(env);
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break;
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return 0;
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case SYSREG_PMUSERENR_EL0:
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env->cp15.c9_pmuserenr = val & 0xf;
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break;
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return 0;
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case SYSREG_PMCNTENSET_EL0:
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env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env));
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break;
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return 0;
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case SYSREG_PMCNTENCLR_EL0:
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env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env));
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break;
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return 0;
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case SYSREG_PMINTENCLR_EL1:
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pmu_op_start(env);
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env->cp15.c9_pminten |= val;
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pmu_op_finish(env);
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break;
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return 0;
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case SYSREG_PMOVSCLR_EL0:
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pmu_op_start(env);
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env->cp15.c9_pmovsr &= ~val;
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pmu_op_finish(env);
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break;
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return 0;
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case SYSREG_PMSWINC_EL0:
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pmu_op_start(env);
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pmswinc_write(env, val);
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pmu_op_finish(env);
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break;
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return 0;
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case SYSREG_PMSELR_EL0:
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env->cp15.c9_pmselr = val & 0x1f;
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break;
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return 0;
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case SYSREG_PMCCFILTR_EL0:
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pmu_op_start(env);
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env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0;
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pmu_op_finish(env);
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break;
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return 0;
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case SYSREG_OSLAR_EL1:
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env->cp15.oslsr_el1 = val & 1;
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break;
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return 0;
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case SYSREG_OSDLR_EL1:
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/* Dummy register */
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break;
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return 0;
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case SYSREG_ICC_AP0R0_EL1:
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case SYSREG_ICC_AP0R1_EL1:
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case SYSREG_ICC_AP0R2_EL1:
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@ -1591,10 +1579,10 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
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if (!hvf_sysreg_write_cp(cpu, reg, val)) {
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hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
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}
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break;
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return 0;
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case SYSREG_MDSCR_EL1:
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env->cp15.mdscr_el1 = val;
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break;
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return 0;
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case SYSREG_DBGBVR0_EL1:
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case SYSREG_DBGBVR1_EL1:
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case SYSREG_DBGBVR2_EL1:
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@ -1612,7 +1600,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
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case SYSREG_DBGBVR14_EL1:
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case SYSREG_DBGBVR15_EL1:
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env->cp15.dbgbvr[SYSREG_CRM(reg)] = val;
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break;
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return 0;
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case SYSREG_DBGBCR0_EL1:
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case SYSREG_DBGBCR1_EL1:
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case SYSREG_DBGBCR2_EL1:
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@ -1630,7 +1618,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
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case SYSREG_DBGBCR14_EL1:
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case SYSREG_DBGBCR15_EL1:
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env->cp15.dbgbcr[SYSREG_CRM(reg)] = val;
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break;
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return 0;
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case SYSREG_DBGWVR0_EL1:
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case SYSREG_DBGWVR1_EL1:
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case SYSREG_DBGWVR2_EL1:
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@ -1648,7 +1636,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
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case SYSREG_DBGWVR14_EL1:
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case SYSREG_DBGWVR15_EL1:
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env->cp15.dbgwvr[SYSREG_CRM(reg)] = val;
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break;
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return 0;
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case SYSREG_DBGWCR0_EL1:
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case SYSREG_DBGWCR1_EL1:
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case SYSREG_DBGWCR2_EL1:
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@ -1666,20 +1654,18 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
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case SYSREG_DBGWCR14_EL1:
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case SYSREG_DBGWCR15_EL1:
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env->cp15.dbgwcr[SYSREG_CRM(reg)] = val;
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break;
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default:
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cpu_synchronize_state(cpu);
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trace_hvf_unhandled_sysreg_write(env->pc, reg,
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SYSREG_OP0(reg),
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SYSREG_OP1(reg),
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SYSREG_CRN(reg),
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SYSREG_CRM(reg),
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SYSREG_OP2(reg));
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hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
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return 1;
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return 0;
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}
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return 0;
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cpu_synchronize_state(cpu);
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trace_hvf_unhandled_sysreg_write(env->pc, reg,
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SYSREG_OP0(reg),
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SYSREG_OP1(reg),
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SYSREG_CRN(reg),
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SYSREG_CRM(reg),
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SYSREG_OP2(reg));
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hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
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return 1;
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}
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static int hvf_inject_interrupts(CPUState *cpu)
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@ -1944,7 +1930,17 @@ int hvf_vcpu_exec(CPUState *cpu)
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int sysreg_ret = 0;
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if (isread) {
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sysreg_ret = hvf_sysreg_read(cpu, reg, rt);
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sysreg_ret = hvf_sysreg_read(cpu, reg, &val);
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if (!sysreg_ret) {
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trace_hvf_sysreg_read(reg,
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SYSREG_OP0(reg),
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SYSREG_OP1(reg),
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SYSREG_CRN(reg),
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SYSREG_CRM(reg),
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SYSREG_OP2(reg),
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val);
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hvf_set_reg(cpu, rt, val);
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}
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} else {
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val = hvf_get_reg(cpu, rt);
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sysreg_ret = hvf_sysreg_write(cpu, reg, val);
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