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target-mips: add 24KEc CPU definition

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Define a new CPU definition supporting 24KEc cores, similar to
the existing 24Kc, but with added support for DSP instructions
and MIPS16e (and without FPU).

Signed-off-by: André Draszik <git@andred.net>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
André Draszik 2016-07-26 00:42:45 +01:00 committed by Leon Alrae
parent 430da7a81d
commit e9deaad8a5
1 changed files with 22 additions and 0 deletions
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22
target-mips/translate_init.c
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@ -255,6 +255,28 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
.mmu_type = MMU_TYPE_R4000, .mmu_type = MMU_TYPE_R4000,
}, },
{
.name = "24KEc",
.CP0_PRid = 0x00019600,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
(MMU_TYPE_R4000 << CP0C0_MT),
.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
.CCRes = 2,
/* we have a DSP, but no FPU */
.CP0_Status_rw_bitmask = 0x1378FF1F,
.SEGBITS = 32,
.PABITS = 32,
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
.mmu_type = MMU_TYPE_R4000,
},
{ {
.name = "24Kf", .name = "24Kf",
.CP0_PRid = 0x00019300, .CP0_PRid = 0x00019300,