target/microblaze: Unwind properly when raising divide-by-zero
Restore the correct pc when raising divide-by-zero. Also, the MSR[DZO] bit is sticky -- it is not cleared with a successful divide. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1,7 +1,7 @@
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DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
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DEF_HELPER_3(divs, i32, env, i32, i32)
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DEF_HELPER_3(divu, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32)
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DEF_HELPER_3(fadd, i32, env, i32, i32)
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DEF_HELPER_3(frsub, i32, env, i32, i32)
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@ -69,26 +69,27 @@ void helper_raise_exception(CPUMBState *env, uint32_t index)
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cpu_loop_exit(cs);
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}
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static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
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static bool check_divz(CPUMBState *env, uint32_t a, uint32_t b, uintptr_t ra)
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{
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MicroBlazeCPU *cpu = env_archcpu(env);
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if (b == 0) {
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if (unlikely(b == 0)) {
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env->msr |= MSR_DZ;
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if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) {
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if ((env->msr & MSR_EE) &&
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env_archcpu(env)->cfg.div_zero_exception) {
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CPUState *cs = env_cpu(env);
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env->esr = ESR_EC_DIVZERO;
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helper_raise_exception(env, EXCP_HW_EXCP);
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cs->exception_index = EXCP_HW_EXCP;
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cpu_loop_exit_restore(cs, ra);
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}
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return 0;
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return false;
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}
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env->msr &= ~MSR_DZ;
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return 1;
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return true;
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}
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uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
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{
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if (!div_prepare(env, a, b)) {
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if (!check_divz(env, a, b, GETPC())) {
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return 0;
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}
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return (int32_t)a / (int32_t)b;
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@ -96,7 +97,7 @@ uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
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uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
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{
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if (!div_prepare(env, a, b)) {
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if (!check_divz(env, a, b, GETPC())) {
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return 0;
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}
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return a / b;
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