MIPS patches queue
- Fix CACHEE opcode - Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes - Remove isa_get_irq() call in PIIX4 south bridge - Add various missing fields to the MIPS CPU migration vmstate - Lot of code moved around to allow TCG or KVM only builds - Restrict non-virtualized machines to TCG - Add KVM mips64el cross-build jobs to gitlab-ci -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmCOvbMACgkQ4+MsLN6t wN4G0A/+MJ9UyVn15f9J1BtPaIcqKi0H47Ry4Pyr7wsV/CxTKApj2uGGbO4NoOLo GJGurlr6T3QgETnJZ+yXfkAzPZfuBYAEK6v7QhXs5xqXipvDL9VSUAJPXWNJbE64 b7YAQjAeePnOnFe1/b5f6te0krlIFqZ3tUj8oCJF1GSiwwi7mOrV56pRnuGPNlvT lkQRAcqlp7qA8EzLisjYd4Ovw/3WvIr58r2Y3pZi3lisKS9yzD71eaqAKmL6dtWa zlwniVxB9qal9DgAyRJzB5B586xHycysOEiLYPzRLrbZ0KtnfsViKdHJ5Z8MYtC4 RAu5UImXL5FCK/8gHWKyT5MCu43dk1cR7LbeGyj4VNZWhHrwCHvmpzUXUdb7i3PC QY1WR7kNmV85FspbzdH5LDfHeRhWenUDsa/ltMUqyhYETv/VL0KnJdA2sx70rKZ+ XPM6OmrF5phxJ2ejfof4M1z9w4M68x/KcYwaH27qS8Y70M29W8bQdfvRXSsOlV7Y p9LnCAlwjEm0JoKMj5V0DeJBTR8o/WSXZnvvc+e+nMDFS5Fkt0HQBC+deUFC2g6d PCyWlasPKWOZ2Z2Ej3rPSyuiDmM+ajw+IiEw074mgxLJNdyKDCWqz06SZDEzwLPp olKQ4AHHsaoRuyaAlw7sHsEWVn8OMhqyoy+M4HMNviAT8NegCmY= =AW2n -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/philmd/tags/mips-20210502' into staging MIPS patches queue - Fix CACHEE opcode - Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes - Remove isa_get_irq() call in PIIX4 south bridge - Add various missing fields to the MIPS CPU migration vmstate - Lot of code moved around to allow TCG or KVM only builds - Restrict non-virtualized machines to TCG - Add KVM mips64el cross-build jobs to gitlab-ci # gpg: Signature made Sun 02 May 2021 15:56:51 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/mips-20210502: (36 commits) gitlab-ci: Add KVM mips64el cross-build jobs hw/mips: Restrict non-virtualized machines to TCG target/mips: Move TCG source files under tcg/ sub directory target/mips: Move CP0 helpers to sysemu/cp0.c target/mips: Move exception management code to exception.c target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c target/mips: Move helper_cache() to tcg/sysemu/special_helper.c target/mips: Move Special opcodes to tcg/sysemu/special_helper.c target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope target/mips: Move tlb_helper.c to tcg/sysemu/ target/mips: Restrict mmu_init() to TCG target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG target/mips: Move physical addressing code to sysemu/physaddr.c target/mips: Move sysemu specific files under sysemu/ subfolder target/mips: Move cpu_signal_handler definition around target/mips: Add simple user-mode mips_cpu_tlb_fill() target/mips: Add simple user-mode mips_cpu_do_interrupt() target/mips: Introduce tcg-internal.h for TCG specific declarations meson: Introduce meson_user_arch source set for arch-specific user-mode ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
e93d8bcf9d
@ -176,6 +176,14 @@ cross-s390x-kvm-only:
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IMAGE: debian-s390x-cross
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ACCEL_CONFIGURE_OPTS: --disable-tcg
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cross-mips64el-kvm-only:
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extends: .cross_accel_build_job
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needs:
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job: mips64el-debian-cross-container
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variables:
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IMAGE: debian-mips64el-cross
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ACCEL_CONFIGURE_OPTS: --disable-tcg --target-list=mips64el-softmmu
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cross-win32-system:
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extends: .cross_system_build_job
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needs:
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|
@ -404,7 +404,8 @@ F: target/arm/kvm.c
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MIPS KVM CPUs
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M: Huacai Chen <chenhuacai@kernel.org>
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S: Odd Fixes
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F: target/mips/kvm.c
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F: target/mips/kvm*
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F: target/mips/sysemu/
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PPC KVM CPUs
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M: David Gibson <david@gibson.dropbear.id.au>
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|
@ -268,8 +268,9 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
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pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
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if (smbus) {
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*smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
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isa_get_irq(NULL, 9), NULL, 0, NULL);
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}
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qdev_get_gpio_in_named(dev, "isa", 9),
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NULL, 0, NULL);
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}
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return dev;
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}
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@ -1,12 +1,15 @@
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mips_ss = ss.source_set()
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mips_ss.add(files('bootloader.c', 'mips_int.c'))
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mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c'))
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mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
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mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c'))
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mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
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mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
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mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c'))
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mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt])
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mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c'))
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if 'CONFIG_TCG' in config_all
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mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
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mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c'))
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mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
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mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt])
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endif
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hw_arch += {'mips': mips_ss}
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@ -1751,6 +1751,7 @@ modules = {}
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hw_arch = {}
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target_arch = {}
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target_softmmu_arch = {}
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target_user_arch = {}
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###############
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# Trace files #
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@ -2168,6 +2169,11 @@ foreach target : target_dirs
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abi = config_target['TARGET_ABI_DIR']
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target_type='user'
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qemu_target_name = 'qemu-' + target_name
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if arch in target_user_arch
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t = target_user_arch[arch].apply(config_target, strict: false)
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arch_srcs += t.sources()
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arch_deps += t.dependencies()
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endif
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if 'CONFIG_LINUX_USER' in config_target
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base_dir = 'linux-user'
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target_inc += include_directories('linux-user/host/' / config_host['ARCH'])
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|
@ -35,155 +35,84 @@
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#include "qapi/qapi-commands-machine-target.h"
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#include "fpu_helper.h"
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#if !defined(CONFIG_USER_ONLY)
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/* Called for updates to CP0_Status. */
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void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
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{
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int32_t tcstatus, *tcst;
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uint32_t v = cpu->CP0_Status;
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uint32_t cu, mx, asid, ksu;
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uint32_t mask = ((1 << CP0TCSt_TCU3)
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| (1 << CP0TCSt_TCU2)
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| (1 << CP0TCSt_TCU1)
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| (1 << CP0TCSt_TCU0)
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| (1 << CP0TCSt_TMX)
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| (3 << CP0TCSt_TKSU)
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| (0xff << CP0TCSt_TASID));
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cu = (v >> CP0St_CU0) & 0xf;
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mx = (v >> CP0St_MX) & 0x1;
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ksu = (v >> CP0St_KSU) & 0x3;
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asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
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tcstatus = cu << CP0TCSt_TCU0;
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tcstatus |= mx << CP0TCSt_TMX;
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tcstatus |= ksu << CP0TCSt_TKSU;
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tcstatus |= asid;
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if (tc == cpu->current_tc) {
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tcst = &cpu->active_tc.CP0_TCStatus;
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} else {
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tcst = &cpu->tcs[tc].CP0_TCStatus;
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}
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*tcst &= ~mask;
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*tcst |= tcstatus;
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compute_hflags(cpu);
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}
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void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = env->CP0_Status_rw_bitmask;
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target_ulong old = env->CP0_Status;
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if (env->insn_flags & ISA_MIPS_R6) {
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bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
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#if defined(TARGET_MIPS64)
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uint32_t ksux = (1 << CP0St_KX) & val;
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ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
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ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
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val = (val & ~(7 << CP0St_UX)) | ksux;
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#endif
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if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
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mask &= ~(3 << CP0St_KSU);
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}
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mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
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}
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env->CP0_Status = (old & ~mask) | (val & mask);
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#if defined(TARGET_MIPS64)
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if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
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/* Access to at least one of the 64-bit segments has been disabled */
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tlb_flush(env_cpu(env));
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}
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#endif
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if (ase_mt_available(env)) {
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sync_c0_status(env, env, env->current_tc);
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} else {
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compute_hflags(env);
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}
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}
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void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = 0x00C00300;
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uint32_t old = env->CP0_Cause;
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int i;
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if (env->insn_flags & ISA_MIPS_R2) {
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mask |= 1 << CP0Ca_DC;
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}
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if (env->insn_flags & ISA_MIPS_R6) {
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mask &= ~((1 << CP0Ca_WP) & val);
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}
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env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
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if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
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if (env->CP0_Cause & (1 << CP0Ca_DC)) {
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cpu_mips_stop_count(env);
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} else {
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cpu_mips_start_count(env);
|
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}
|
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}
|
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|
||||
/* Set/reset software interrupts */
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for (i = 0 ; i < 2 ; i++) {
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if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
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cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
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}
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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static const char * const excp_names[EXCP_LAST + 1] = {
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[EXCP_RESET] = "reset",
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[EXCP_SRESET] = "soft reset",
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[EXCP_DSS] = "debug single step",
|
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[EXCP_DINT] = "debug interrupt",
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[EXCP_NMI] = "non-maskable interrupt",
|
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[EXCP_MCHECK] = "machine check",
|
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[EXCP_EXT_INTERRUPT] = "interrupt",
|
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[EXCP_DFWATCH] = "deferred watchpoint",
|
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[EXCP_DIB] = "debug instruction breakpoint",
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[EXCP_IWATCH] = "instruction fetch watchpoint",
|
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[EXCP_AdEL] = "address error load",
|
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[EXCP_AdES] = "address error store",
|
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[EXCP_TLBF] = "TLB refill",
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[EXCP_IBE] = "instruction bus error",
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[EXCP_DBp] = "debug breakpoint",
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[EXCP_SYSCALL] = "syscall",
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[EXCP_BREAK] = "break",
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[EXCP_CpU] = "coprocessor unusable",
|
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[EXCP_RI] = "reserved instruction",
|
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[EXCP_OVERFLOW] = "arithmetic overflow",
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[EXCP_TRAP] = "trap",
|
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[EXCP_FPE] = "floating point",
|
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[EXCP_DDBS] = "debug data break store",
|
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[EXCP_DWATCH] = "data watchpoint",
|
||||
[EXCP_LTLBL] = "TLB modify",
|
||||
[EXCP_TLBL] = "TLB load",
|
||||
[EXCP_TLBS] = "TLB store",
|
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[EXCP_DBE] = "data bus error",
|
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[EXCP_DDBL] = "debug data break load",
|
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[EXCP_THREAD] = "thread",
|
||||
[EXCP_MDMX] = "MDMX",
|
||||
[EXCP_C2E] = "precise coprocessor 2",
|
||||
[EXCP_CACHE] = "cache error",
|
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[EXCP_TLBXI] = "TLB execute-inhibit",
|
||||
[EXCP_TLBRI] = "TLB read-inhibit",
|
||||
[EXCP_MSADIS] = "MSA disabled",
|
||||
[EXCP_MSAFPE] = "MSA floating point",
|
||||
const char regnames[32][4] = {
|
||||
"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
|
||||
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
|
||||
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
|
||||
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
|
||||
};
|
||||
|
||||
const char *mips_exception_name(int32_t exception)
|
||||
static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64)
|
||||
{
|
||||
if (exception < 0 || exception > EXCP_LAST) {
|
||||
return "unknown";
|
||||
if (is_fpu64) {
|
||||
qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n",
|
||||
fpr->w[FP_ENDIAN_IDX], fpr->d,
|
||||
(double)fpr->fd,
|
||||
(double)fpr->fs[FP_ENDIAN_IDX],
|
||||
(double)fpr->fs[!FP_ENDIAN_IDX]);
|
||||
} else {
|
||||
fpr_t tmp;
|
||||
|
||||
tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX];
|
||||
tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX];
|
||||
qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n",
|
||||
tmp.w[FP_ENDIAN_IDX], tmp.d,
|
||||
(double)tmp.fd,
|
||||
(double)tmp.fs[FP_ENDIAN_IDX],
|
||||
(double)tmp.fs[!FP_ENDIAN_IDX]);
|
||||
}
|
||||
}
|
||||
|
||||
static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
|
||||
{
|
||||
int i;
|
||||
bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
|
||||
|
||||
qemu_fprintf(f,
|
||||
"CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
|
||||
env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
|
||||
get_float_exception_flags(&env->active_fpu.fp_status));
|
||||
for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
|
||||
qemu_fprintf(f, "%3s: ", fregnames[i]);
|
||||
fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64);
|
||||
}
|
||||
}
|
||||
|
||||
static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
int i;
|
||||
|
||||
qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
|
||||
" LO=0x" TARGET_FMT_lx " ds %04x "
|
||||
TARGET_FMT_lx " " TARGET_FMT_ld "\n",
|
||||
env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
|
||||
env->hflags, env->btarget, env->bcond);
|
||||
for (i = 0; i < 32; i++) {
|
||||
if ((i & 3) == 0) {
|
||||
qemu_fprintf(f, "GPR%02d:", i);
|
||||
}
|
||||
qemu_fprintf(f, " %s " TARGET_FMT_lx,
|
||||
regnames[i], env->active_tc.gpr[i]);
|
||||
if ((i & 3) == 3) {
|
||||
qemu_fprintf(f, "\n");
|
||||
}
|
||||
}
|
||||
|
||||
qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
|
||||
TARGET_FMT_lx "\n",
|
||||
env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
|
||||
qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
|
||||
PRIx64 "\n",
|
||||
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
|
||||
qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
|
||||
env->CP0_Config2, env->CP0_Config3);
|
||||
qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
|
||||
env->CP0_Config4, env->CP0_Config5);
|
||||
if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
|
||||
fpu_dump_state(env, f, flags);
|
||||
}
|
||||
return excp_names[exception];
|
||||
}
|
||||
|
||||
void cpu_set_exception_base(int vp_index, target_ulong address)
|
||||
@ -192,101 +121,13 @@ void cpu_set_exception_base(int vp_index, target_ulong address)
|
||||
vp->env.exception_base = address;
|
||||
}
|
||||
|
||||
target_ulong exception_resume_pc(CPUMIPSState *env)
|
||||
{
|
||||
target_ulong bad_pc;
|
||||
target_ulong isa_mode;
|
||||
|
||||
isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
|
||||
bad_pc = env->active_tc.PC | isa_mode;
|
||||
if (env->hflags & MIPS_HFLAG_BMASK) {
|
||||
/*
|
||||
* If the exception was raised from a delay slot, come back to
|
||||
* the jump.
|
||||
*/
|
||||
bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
|
||||
}
|
||||
|
||||
return bad_pc;
|
||||
}
|
||||
|
||||
bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
||||
{
|
||||
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
|
||||
if (cpu_mips_hw_interrupts_enabled(env) &&
|
||||
cpu_mips_hw_interrupts_pending(env)) {
|
||||
/* Raise it */
|
||||
cs->exception_index = EXCP_EXT_INTERRUPT;
|
||||
env->error_code = 0;
|
||||
mips_cpu_do_interrupt(cs);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
|
||||
uint32_t exception,
|
||||
int error_code,
|
||||
uintptr_t pc)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
|
||||
qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
|
||||
__func__, exception, mips_exception_name(exception),
|
||||
error_code);
|
||||
cs->exception_index = exception;
|
||||
env->error_code = error_code;
|
||||
|
||||
cpu_loop_exit_restore(cs, pc);
|
||||
}
|
||||
|
||||
static void mips_cpu_set_pc(CPUState *cs, vaddr value)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
|
||||
env->active_tc.PC = value & ~(target_ulong)1;
|
||||
if (value & 1) {
|
||||
env->hflags |= MIPS_HFLAG_M16;
|
||||
} else {
|
||||
env->hflags &= ~(MIPS_HFLAG_M16);
|
||||
}
|
||||
mips_env_set_pc(&cpu->env, value);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TCG
|
||||
static void mips_cpu_synchronize_from_tb(CPUState *cs,
|
||||
const TranslationBlock *tb)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
|
||||
env->active_tc.PC = tb->pc;
|
||||
env->hflags &= ~MIPS_HFLAG_BMASK;
|
||||
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
|
||||
}
|
||||
|
||||
# ifndef CONFIG_USER_ONLY
|
||||
static bool mips_io_recompile_replay_branch(CPUState *cs,
|
||||
const TranslationBlock *tb)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
|
||||
if ((env->hflags & MIPS_HFLAG_BMASK) != 0
|
||||
&& env->active_tc.PC != tb->pc) {
|
||||
env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
|
||||
env->hflags &= ~MIPS_HFLAG_BMASK;
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
# endif /* !CONFIG_USER_ONLY */
|
||||
#endif /* CONFIG_TCG */
|
||||
|
||||
static bool mips_cpu_has_work(CPUState *cs)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
@ -634,7 +475,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
|
||||
|
||||
env->exception_base = (int32_t)0xBFC00000;
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
|
||||
mmu_init(env, env->cpu_model);
|
||||
#endif
|
||||
fpu_init(env, env->cpu_model);
|
||||
|
25
target/mips/fpu.c
Normal file
25
target/mips/fpu.c
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Helpers for emulation of FPU-related MIPS instructions.
|
||||
*
|
||||
* Copyright (C) 2004-2005 Jocelyn Mayer
|
||||
*
|
||||
* SPDX-License-Identifier: LGPL-2.1-or-later
|
||||
*/
|
||||
#include "qemu/osdep.h"
|
||||
#include "fpu/softfloat-helpers.h"
|
||||
#include "fpu_helper.h"
|
||||
|
||||
/* convert MIPS rounding mode in FCR31 to IEEE library */
|
||||
const FloatRoundMode ieee_rm[4] = {
|
||||
float_round_nearest_even,
|
||||
float_round_to_zero,
|
||||
float_round_up,
|
||||
float_round_down
|
||||
};
|
||||
|
||||
const char fregnames[32][4] = {
|
||||
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
|
||||
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
|
||||
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
|
||||
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
|
||||
};
|
@ -2,10 +2,6 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int)
|
||||
DEF_HELPER_2(raise_exception, noreturn, env, i32)
|
||||
DEF_HELPER_1(raise_exception_debug, noreturn, env)
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
DEF_HELPER_1(do_semihosting, void, env)
|
||||
#endif
|
||||
|
||||
#ifdef TARGET_MIPS64
|
||||
DEF_HELPER_4(sdl, void, env, tl, tl, int)
|
||||
DEF_HELPER_4(sdr, void, env, tl, tl, int)
|
||||
@ -42,164 +38,6 @@ DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
|
||||
|
||||
DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
/* CP0 helpers */
|
||||
DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
|
||||
DEF_HELPER_1(mfc0_mvpconf0, tl, env)
|
||||
DEF_HELPER_1(mfc0_mvpconf1, tl, env)
|
||||
DEF_HELPER_1(mftc0_vpecontrol, tl, env)
|
||||
DEF_HELPER_1(mftc0_vpeconf0, tl, env)
|
||||
DEF_HELPER_1(mfc0_random, tl, env)
|
||||
DEF_HELPER_1(mfc0_tcstatus, tl, env)
|
||||
DEF_HELPER_1(mftc0_tcstatus, tl, env)
|
||||
DEF_HELPER_1(mfc0_tcbind, tl, env)
|
||||
DEF_HELPER_1(mftc0_tcbind, tl, env)
|
||||
DEF_HELPER_1(mfc0_tcrestart, tl, env)
|
||||
DEF_HELPER_1(mftc0_tcrestart, tl, env)
|
||||
DEF_HELPER_1(mfc0_tchalt, tl, env)
|
||||
DEF_HELPER_1(mftc0_tchalt, tl, env)
|
||||
DEF_HELPER_1(mfc0_tccontext, tl, env)
|
||||
DEF_HELPER_1(mftc0_tccontext, tl, env)
|
||||
DEF_HELPER_1(mfc0_tcschedule, tl, env)
|
||||
DEF_HELPER_1(mftc0_tcschedule, tl, env)
|
||||
DEF_HELPER_1(mfc0_tcschefback, tl, env)
|
||||
DEF_HELPER_1(mftc0_tcschefback, tl, env)
|
||||
DEF_HELPER_1(mfc0_count, tl, env)
|
||||
DEF_HELPER_1(mfc0_saar, tl, env)
|
||||
DEF_HELPER_1(mfhc0_saar, tl, env)
|
||||
DEF_HELPER_1(mftc0_entryhi, tl, env)
|
||||
DEF_HELPER_1(mftc0_status, tl, env)
|
||||
DEF_HELPER_1(mftc0_cause, tl, env)
|
||||
DEF_HELPER_1(mftc0_epc, tl, env)
|
||||
DEF_HELPER_1(mftc0_ebase, tl, env)
|
||||
DEF_HELPER_2(mftc0_configx, tl, env, tl)
|
||||
DEF_HELPER_1(mfc0_lladdr, tl, env)
|
||||
DEF_HELPER_1(mfc0_maar, tl, env)
|
||||
DEF_HELPER_1(mfhc0_maar, tl, env)
|
||||
DEF_HELPER_2(mfc0_watchlo, tl, env, i32)
|
||||
DEF_HELPER_2(mfc0_watchhi, tl, env, i32)
|
||||
DEF_HELPER_2(mfhc0_watchhi, tl, env, i32)
|
||||
DEF_HELPER_1(mfc0_debug, tl, env)
|
||||
DEF_HELPER_1(mftc0_debug, tl, env)
|
||||
#ifdef TARGET_MIPS64
|
||||
DEF_HELPER_1(dmfc0_tcrestart, tl, env)
|
||||
DEF_HELPER_1(dmfc0_tchalt, tl, env)
|
||||
DEF_HELPER_1(dmfc0_tccontext, tl, env)
|
||||
DEF_HELPER_1(dmfc0_tcschedule, tl, env)
|
||||
DEF_HELPER_1(dmfc0_tcschefback, tl, env)
|
||||
DEF_HELPER_1(dmfc0_lladdr, tl, env)
|
||||
DEF_HELPER_1(dmfc0_maar, tl, env)
|
||||
DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
|
||||
DEF_HELPER_2(dmfc0_watchhi, tl, env, i32)
|
||||
DEF_HELPER_1(dmfc0_saar, tl, env)
|
||||
#endif /* TARGET_MIPS64 */
|
||||
|
||||
DEF_HELPER_2(mtc0_index, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_vpecontrol, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_vpecontrol, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_vpeconf0, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_vpeconf0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_vpeconf1, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_yqmask, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_vpeopt, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_entrylo0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tcstatus, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tcstatus, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tcbind, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tcbind, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tcrestart, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tcrestart, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tchalt, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tchalt, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tccontext, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tccontext, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tcschedule, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tcschedule, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tcschefback, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tcschefback, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_entrylo1, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_context, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_memorymapid, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_pagemask, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_pagegrain, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_segctl0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_segctl1, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_segctl2, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_pwfield, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_pwsize, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_wired, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsconf0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsconf1, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsconf2, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsconf3, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_hwrena, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_pwctl, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_count, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_saari, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_saar, void, env, tl)
|
||||
DEF_HELPER_2(mthc0_saar, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_entryhi, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_entryhi, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_compare, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_status, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_status, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_intctl, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsctl, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_cause, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_cause, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_ebase, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_ebase, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_config0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_config2, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_config3, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_config4, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_config5, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_lladdr, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_maar, void, env, tl)
|
||||
DEF_HELPER_2(mthc0_maar, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_maari, void, env, tl)
|
||||
DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
|
||||
DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
|
||||
DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32)
|
||||
DEF_HELPER_2(mtc0_xcontext, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_framemask, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_debug, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_debug, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_performance0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_errctl, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_taglo, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_datalo, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_taghi, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_datahi, void, env, tl)
|
||||
|
||||
#if defined(TARGET_MIPS64)
|
||||
DEF_HELPER_2(dmtc0_entrylo0, void, env, i64)
|
||||
DEF_HELPER_2(dmtc0_entrylo1, void, env, i64)
|
||||
#endif
|
||||
|
||||
/* MIPS MT functions */
|
||||
DEF_HELPER_2(mftgpr, tl, env, i32)
|
||||
DEF_HELPER_2(mftlo, tl, env, i32)
|
||||
DEF_HELPER_2(mfthi, tl, env, i32)
|
||||
DEF_HELPER_2(mftacx, tl, env, i32)
|
||||
DEF_HELPER_1(mftdsp, tl, env)
|
||||
DEF_HELPER_3(mttgpr, void, env, tl, i32)
|
||||
DEF_HELPER_3(mttlo, void, env, tl, i32)
|
||||
DEF_HELPER_3(mtthi, void, env, tl, i32)
|
||||
DEF_HELPER_3(mttacx, void, env, tl, i32)
|
||||
DEF_HELPER_2(mttdsp, void, env, tl)
|
||||
DEF_HELPER_0(dmt, tl)
|
||||
DEF_HELPER_0(emt, tl)
|
||||
DEF_HELPER_1(dvpe, tl, env)
|
||||
DEF_HELPER_1(evpe, tl, env)
|
||||
|
||||
/* R6 Multi-threading */
|
||||
DEF_HELPER_1(dvp, tl, env)
|
||||
DEF_HELPER_1(evp, tl, env)
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
/* microMIPS functions */
|
||||
DEF_HELPER_4(lwm, void, env, tl, tl, i32)
|
||||
DEF_HELPER_4(swm, void, env, tl, tl, i32)
|
||||
@ -364,21 +202,6 @@ FOP_PROTO(sune)
|
||||
FOP_PROTO(sne)
|
||||
#undef FOP_PROTO
|
||||
|
||||
/* Special functions */
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
DEF_HELPER_1(tlbwi, void, env)
|
||||
DEF_HELPER_1(tlbwr, void, env)
|
||||
DEF_HELPER_1(tlbp, void, env)
|
||||
DEF_HELPER_1(tlbr, void, env)
|
||||
DEF_HELPER_1(tlbinv, void, env)
|
||||
DEF_HELPER_1(tlbinvf, void, env)
|
||||
DEF_HELPER_1(di, tl, env)
|
||||
DEF_HELPER_1(ei, tl, env)
|
||||
DEF_HELPER_1(eret, void, env)
|
||||
DEF_HELPER_1(eretnc, void, env)
|
||||
DEF_HELPER_1(deret, void, env)
|
||||
DEF_HELPER_3(ginvt, void, env, tl, i32)
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
DEF_HELPER_1(rdhwr_cpunum, tl, env)
|
||||
DEF_HELPER_1(rdhwr_synci_step, tl, env)
|
||||
DEF_HELPER_1(rdhwr_cc, tl, env)
|
||||
@ -781,6 +604,8 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env)
|
||||
DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env)
|
||||
DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
|
||||
|
||||
DEF_HELPER_3(cache, void, env, tl, i32)
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
#include "tcg/sysemu_helper.h.inc"
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
#include "msa_helper.h.inc"
|
||||
#include "tcg/msa_helper.h.inc"
|
||||
|
@ -9,6 +9,9 @@
|
||||
#define MIPS_INTERNAL_H
|
||||
|
||||
#include "exec/memattrs.h"
|
||||
#ifdef CONFIG_TCG
|
||||
#include "tcg/tcg-internal.h"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MMU types, the first four entries have the same layout as the
|
||||
@ -71,21 +74,41 @@ struct mips_def_t {
|
||||
int32_t SAARP;
|
||||
};
|
||||
|
||||
extern const char regnames[32][4];
|
||||
extern const char fregnames[32][4];
|
||||
|
||||
extern const struct mips_def_t mips_defs[];
|
||||
extern const int mips_defs_number;
|
||||
|
||||
void mips_cpu_do_interrupt(CPUState *cpu);
|
||||
bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
|
||||
void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
|
||||
hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
||||
int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
|
||||
int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
|
||||
void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
|
||||
MMUAccessType access_type,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
|
||||
#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
|
||||
#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
|
||||
#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
|
||||
#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
|
||||
#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
|
||||
|
||||
#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
|
||||
#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
enum {
|
||||
TLBRET_XI = -6,
|
||||
TLBRET_RI = -5,
|
||||
TLBRET_DIRTY = -4,
|
||||
TLBRET_INVALID = -3,
|
||||
TLBRET_NOMATCH = -2,
|
||||
TLBRET_BADADDR = -1,
|
||||
TLBRET_MATCH = 0
|
||||
};
|
||||
|
||||
int get_physical_address(CPUMIPSState *env, hwaddr *physical,
|
||||
int *prot, target_ulong real_address,
|
||||
MMUAccessType access_type, int mmu_idx);
|
||||
hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
||||
|
||||
typedef struct r4k_tlb_t r4k_tlb_t;
|
||||
struct r4k_tlb_t {
|
||||
target_ulong VPN;
|
||||
@ -125,36 +148,16 @@ struct CPUMIPSTLBContext {
|
||||
} mmu;
|
||||
};
|
||||
|
||||
int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
|
||||
target_ulong address, MMUAccessType access_type);
|
||||
int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
|
||||
target_ulong address, MMUAccessType access_type);
|
||||
int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
|
||||
target_ulong address, MMUAccessType access_type);
|
||||
void r4k_helper_tlbwi(CPUMIPSState *env);
|
||||
void r4k_helper_tlbwr(CPUMIPSState *env);
|
||||
void r4k_helper_tlbp(CPUMIPSState *env);
|
||||
void r4k_helper_tlbr(CPUMIPSState *env);
|
||||
void r4k_helper_tlbinv(CPUMIPSState *env);
|
||||
void r4k_helper_tlbinvf(CPUMIPSState *env);
|
||||
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
|
||||
uint32_t cpu_mips_get_random(CPUMIPSState *env);
|
||||
void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
|
||||
void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
|
||||
void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
|
||||
|
||||
void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
|
||||
vaddr addr, unsigned size,
|
||||
MMUAccessType access_type,
|
||||
int mmu_idx, MemTxAttrs attrs,
|
||||
MemTxResult response, uintptr_t retaddr);
|
||||
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
|
||||
MMUAccessType access_type);
|
||||
#endif
|
||||
extern const VMStateDescription vmstate_mips_cpu;
|
||||
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
#define cpu_signal_handler cpu_mips_signal_handler
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
extern const VMStateDescription vmstate_mips_cpu;
|
||||
#endif
|
||||
|
||||
static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
|
||||
{
|
||||
return (env->CP0_Status & (1 << CP0St_IE)) &&
|
||||
@ -197,8 +200,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
|
||||
return r;
|
||||
}
|
||||
|
||||
void mips_tcg_init(void);
|
||||
|
||||
void msa_reset(CPUMIPSState *env);
|
||||
|
||||
/* cp0_timer.c */
|
||||
@ -208,14 +209,15 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
|
||||
void cpu_mips_start_count(CPUMIPSState *env);
|
||||
void cpu_mips_stop_count(CPUMIPSState *env);
|
||||
|
||||
/* helper.c */
|
||||
void mmu_init(CPUMIPSState *env, const mips_def_t *def);
|
||||
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
||||
MMUAccessType access_type, int mmu_idx,
|
||||
bool probe, uintptr_t retaddr);
|
||||
|
||||
/* op_helper.c */
|
||||
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
|
||||
static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
|
||||
{
|
||||
env->active_tc.PC = value & ~(target_ulong)1;
|
||||
if (value & 1) {
|
||||
env->hflags |= MIPS_HFLAG_M16;
|
||||
} else {
|
||||
env->hflags &= ~(MIPS_HFLAG_M16);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void restore_pamask(CPUMIPSState *env)
|
||||
{
|
||||
@ -397,21 +399,4 @@ static inline void compute_hflags(CPUMIPSState *env)
|
||||
}
|
||||
}
|
||||
|
||||
void cpu_mips_tlb_flush(CPUMIPSState *env);
|
||||
void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
|
||||
void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
|
||||
void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
|
||||
|
||||
const char *mips_exception_name(int32_t exception);
|
||||
|
||||
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
|
||||
int error_code, uintptr_t pc);
|
||||
|
||||
static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
|
||||
uint32_t exception,
|
||||
uintptr_t pc)
|
||||
{
|
||||
do_raise_exception_err(env, exception, 0, pc);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
@ -1,52 +1,23 @@
|
||||
gen = [
|
||||
decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'),
|
||||
decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
|
||||
decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
|
||||
decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'),
|
||||
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
|
||||
]
|
||||
|
||||
mips_user_ss = ss.source_set()
|
||||
mips_softmmu_ss = ss.source_set()
|
||||
mips_ss = ss.source_set()
|
||||
mips_ss.add(files(
|
||||
'cpu.c',
|
||||
'fpu.c',
|
||||
'gdbstub.c',
|
||||
'msa.c',
|
||||
))
|
||||
mips_tcg_ss = ss.source_set()
|
||||
mips_tcg_ss.add(gen)
|
||||
mips_tcg_ss.add(files(
|
||||
'dsp_helper.c',
|
||||
'fpu_helper.c',
|
||||
'lmmi_helper.c',
|
||||
'msa_helper.c',
|
||||
'msa_translate.c',
|
||||
'op_helper.c',
|
||||
'rel6_translate.c',
|
||||
'tlb_helper.c',
|
||||
'translate.c',
|
||||
'translate_addr_const.c',
|
||||
'txx9_translate.c',
|
||||
))
|
||||
mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files(
|
||||
'tx79_translate.c',
|
||||
))
|
||||
mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files(
|
||||
'mxu_translate.c',
|
||||
))
|
||||
|
||||
if have_system
|
||||
subdir('sysemu')
|
||||
endif
|
||||
|
||||
if 'CONFIG_TCG' in config_all
|
||||
subdir('tcg')
|
||||
endif
|
||||
|
||||
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
|
||||
|
||||
mips_softmmu_ss = ss.source_set()
|
||||
mips_softmmu_ss.add(files(
|
||||
'addr.c',
|
||||
'cp0_timer.c',
|
||||
'machine.c',
|
||||
))
|
||||
mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
|
||||
'cp0_helper.c',
|
||||
'mips-semi.c',
|
||||
))
|
||||
|
||||
mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss])
|
||||
|
||||
target_arch += {'mips': mips_ss}
|
||||
target_softmmu_arch += {'mips': mips_softmmu_ss}
|
||||
target_user_arch += {'mips': mips_user_ss}
|
||||
|
60
target/mips/msa.c
Normal file
60
target/mips/msa.c
Normal file
@ -0,0 +1,60 @@
|
||||
/*
|
||||
* MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
|
||||
*
|
||||
* Copyright (c) 2014 Imagination Technologies
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "internal.h"
|
||||
#include "fpu/softfloat.h"
|
||||
#include "fpu_helper.h"
|
||||
|
||||
void msa_reset(CPUMIPSState *env)
|
||||
{
|
||||
if (!ase_msa_available(env)) {
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USER_ONLY
|
||||
/* MSA access enabled */
|
||||
env->CP0_Config5 |= 1 << CP0C5_MSAEn;
|
||||
env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSA CSR:
|
||||
* - non-signaling floating point exception mode off (NX bit is 0)
|
||||
* - Cause, Enables, and Flags are all 0
|
||||
* - round to nearest / ties to even (RM bits are 0)
|
||||
*/
|
||||
env->active_tc.msacsr = 0;
|
||||
|
||||
restore_msa_fp_status(env);
|
||||
|
||||
/* tininess detected after rounding.*/
|
||||
set_float_detect_tininess(float_tininess_after_rounding,
|
||||
&env->active_tc.msa_fp_status);
|
||||
|
||||
/* clear float_status exception flags */
|
||||
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
|
||||
|
||||
/* clear float_status nan mode */
|
||||
set_default_nan_mode(0, &env->active_tc.msa_fp_status);
|
||||
|
||||
/* set proper signanling bit meaning ("1" means "quiet") */
|
||||
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
|
||||
}
|
File diff suppressed because it is too large
Load Diff
123
target/mips/sysemu/cp0.c
Normal file
123
target/mips/sysemu/cp0.c
Normal file
@ -0,0 +1,123 @@
|
||||
/*
|
||||
* QEMU MIPS CPU
|
||||
*
|
||||
* Copyright (c) 2012 SUSE LINUX Products GmbH
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see
|
||||
* <http://www.gnu.org/licenses/lgpl-2.1.html>
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "internal.h"
|
||||
#include "exec/exec-all.h"
|
||||
|
||||
/* Called for updates to CP0_Status. */
|
||||
void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
|
||||
{
|
||||
int32_t tcstatus, *tcst;
|
||||
uint32_t v = cpu->CP0_Status;
|
||||
uint32_t cu, mx, asid, ksu;
|
||||
uint32_t mask = ((1 << CP0TCSt_TCU3)
|
||||
| (1 << CP0TCSt_TCU2)
|
||||
| (1 << CP0TCSt_TCU1)
|
||||
| (1 << CP0TCSt_TCU0)
|
||||
| (1 << CP0TCSt_TMX)
|
||||
| (3 << CP0TCSt_TKSU)
|
||||
| (0xff << CP0TCSt_TASID));
|
||||
|
||||
cu = (v >> CP0St_CU0) & 0xf;
|
||||
mx = (v >> CP0St_MX) & 0x1;
|
||||
ksu = (v >> CP0St_KSU) & 0x3;
|
||||
asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
|
||||
|
||||
tcstatus = cu << CP0TCSt_TCU0;
|
||||
tcstatus |= mx << CP0TCSt_TMX;
|
||||
tcstatus |= ksu << CP0TCSt_TKSU;
|
||||
tcstatus |= asid;
|
||||
|
||||
if (tc == cpu->current_tc) {
|
||||
tcst = &cpu->active_tc.CP0_TCStatus;
|
||||
} else {
|
||||
tcst = &cpu->tcs[tc].CP0_TCStatus;
|
||||
}
|
||||
|
||||
*tcst &= ~mask;
|
||||
*tcst |= tcstatus;
|
||||
compute_hflags(cpu);
|
||||
}
|
||||
|
||||
void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
|
||||
{
|
||||
uint32_t mask = env->CP0_Status_rw_bitmask;
|
||||
target_ulong old = env->CP0_Status;
|
||||
|
||||
if (env->insn_flags & ISA_MIPS_R6) {
|
||||
bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
|
||||
#if defined(TARGET_MIPS64)
|
||||
uint32_t ksux = (1 << CP0St_KX) & val;
|
||||
ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
|
||||
ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
|
||||
val = (val & ~(7 << CP0St_UX)) | ksux;
|
||||
#endif
|
||||
if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
|
||||
mask &= ~(3 << CP0St_KSU);
|
||||
}
|
||||
mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
|
||||
}
|
||||
|
||||
env->CP0_Status = (old & ~mask) | (val & mask);
|
||||
#if defined(TARGET_MIPS64)
|
||||
if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
|
||||
/* Access to at least one of the 64-bit segments has been disabled */
|
||||
tlb_flush(env_cpu(env));
|
||||
}
|
||||
#endif
|
||||
if (ase_mt_available(env)) {
|
||||
sync_c0_status(env, env, env->current_tc);
|
||||
} else {
|
||||
compute_hflags(env);
|
||||
}
|
||||
}
|
||||
|
||||
void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
|
||||
{
|
||||
uint32_t mask = 0x00C00300;
|
||||
uint32_t old = env->CP0_Cause;
|
||||
int i;
|
||||
|
||||
if (env->insn_flags & ISA_MIPS_R2) {
|
||||
mask |= 1 << CP0Ca_DC;
|
||||
}
|
||||
if (env->insn_flags & ISA_MIPS_R6) {
|
||||
mask &= ~((1 << CP0Ca_WP) & val);
|
||||
}
|
||||
|
||||
env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
|
||||
|
||||
if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
|
||||
if (env->CP0_Cause & (1 << CP0Ca_DC)) {
|
||||
cpu_mips_stop_count(env);
|
||||
} else {
|
||||
cpu_mips_start_count(env);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set/reset software interrupts */
|
||||
for (i = 0 ; i < 2 ; i++) {
|
||||
if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
|
||||
cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
|
||||
}
|
||||
}
|
||||
}
|
@ -81,6 +81,9 @@ const VMStateDescription vmstate_inactive_fpu = {
|
||||
|
||||
static VMStateField vmstate_tc_fields[] = {
|
||||
VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
|
||||
#if defined(TARGET_MIPS64)
|
||||
VMSTATE_UINT64_ARRAY(gpr_hi, TCState, 32),
|
||||
#endif /* TARGET_MIPS64 */
|
||||
VMSTATE_UINTTL(PC, TCState),
|
||||
VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
|
||||
VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
|
||||
@ -95,20 +98,22 @@ static VMStateField vmstate_tc_fields[] = {
|
||||
VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
|
||||
VMSTATE_UINTTL(CP0_UserLocal, TCState),
|
||||
VMSTATE_INT32(msacsr, TCState),
|
||||
VMSTATE_UINTTL_ARRAY(mxu_gpr, TCState, NUMBER_OF_MXU_REGISTERS - 1),
|
||||
VMSTATE_UINTTL(mxu_cr, TCState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
};
|
||||
|
||||
const VMStateDescription vmstate_tc = {
|
||||
.name = "cpu/tc",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.version_id = 2,
|
||||
.minimum_version_id = 2,
|
||||
.fields = vmstate_tc_fields
|
||||
};
|
||||
|
||||
const VMStateDescription vmstate_inactive_tc = {
|
||||
.name = "cpu/inactive_tc",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.version_id = 2,
|
||||
.minimum_version_id = 2,
|
||||
.fields = vmstate_tc_fields
|
||||
};
|
||||
|
||||
@ -213,8 +218,8 @@ const VMStateDescription vmstate_tlb = {
|
||||
|
||||
const VMStateDescription vmstate_mips_cpu = {
|
||||
.name = "cpu",
|
||||
.version_id = 20,
|
||||
.minimum_version_id = 20,
|
||||
.version_id = 21,
|
||||
.minimum_version_id = 21,
|
||||
.post_load = cpu_post_load,
|
||||
.fields = (VMStateField[]) {
|
||||
/* Active TC */
|
||||
@ -241,6 +246,7 @@ const VMStateDescription vmstate_mips_cpu = {
|
||||
|
||||
/* Remaining CP0 registers */
|
||||
VMSTATE_INT32(env.CP0_Index, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_VPControl, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Random, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
|
||||
@ -251,6 +257,7 @@ const VMStateDescription vmstate_mips_cpu = {
|
||||
VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
|
||||
VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
|
||||
VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_GlobalNumber, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
|
||||
@ -286,6 +293,7 @@ const VMStateDescription vmstate_mips_cpu = {
|
||||
VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_CMGCRBase, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
|
||||
@ -305,6 +313,7 @@ const VMStateDescription vmstate_mips_cpu = {
|
||||
VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_ErrCtl, MIPSCPU),
|
||||
VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
|
7
target/mips/sysemu/meson.build
Normal file
7
target/mips/sysemu/meson.build
Normal file
@ -0,0 +1,7 @@
|
||||
mips_softmmu_ss.add(files(
|
||||
'addr.c',
|
||||
'cp0.c',
|
||||
'cp0_timer.c',
|
||||
'machine.c',
|
||||
'physaddr.c',
|
||||
))
|
257
target/mips/sysemu/physaddr.c
Normal file
257
target/mips/sysemu/physaddr.c
Normal file
@ -0,0 +1,257 @@
|
||||
/*
|
||||
* MIPS TLB (Translation lookaside buffer) helpers.
|
||||
*
|
||||
* Copyright (c) 2004-2005 Jocelyn Mayer
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "../internal.h"
|
||||
|
||||
static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
|
||||
{
|
||||
/*
|
||||
* Interpret access control mode and mmu_idx.
|
||||
* AdE? TLB?
|
||||
* AM K S U E K S U E
|
||||
* UK 0 0 1 1 0 0 - - 0
|
||||
* MK 1 0 1 1 0 1 - - !eu
|
||||
* MSK 2 0 0 1 0 1 1 - !eu
|
||||
* MUSK 3 0 0 0 0 1 1 1 !eu
|
||||
* MUSUK 4 0 0 0 0 0 1 1 0
|
||||
* USK 5 0 0 1 0 0 0 - 0
|
||||
* - 6 - - - - - - - -
|
||||
* UUSK 7 0 0 0 0 0 0 0 0
|
||||
*/
|
||||
int32_t adetlb_mask;
|
||||
|
||||
switch (mmu_idx) {
|
||||
case 3: /* ERL */
|
||||
/* If EU is set, always unmapped */
|
||||
if (eu) {
|
||||
return 0;
|
||||
}
|
||||
/* fall through */
|
||||
case MIPS_HFLAG_KM:
|
||||
/* Never AdE, TLB mapped if AM={1,2,3} */
|
||||
adetlb_mask = 0x70000000;
|
||||
goto check_tlb;
|
||||
|
||||
case MIPS_HFLAG_SM:
|
||||
/* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
|
||||
adetlb_mask = 0xc0380000;
|
||||
goto check_ade;
|
||||
|
||||
case MIPS_HFLAG_UM:
|
||||
/* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
|
||||
adetlb_mask = 0xe4180000;
|
||||
/* fall through */
|
||||
check_ade:
|
||||
/* does this AM cause AdE in current execution mode */
|
||||
if ((adetlb_mask << am) < 0) {
|
||||
return TLBRET_BADADDR;
|
||||
}
|
||||
adetlb_mask <<= 8;
|
||||
/* fall through */
|
||||
check_tlb:
|
||||
/* is this AM mapped in current execution mode */
|
||||
return ((adetlb_mask << am) < 0);
|
||||
default:
|
||||
assert(0);
|
||||
return TLBRET_BADADDR;
|
||||
};
|
||||
}
|
||||
|
||||
static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
|
||||
int *prot, target_ulong real_address,
|
||||
MMUAccessType access_type, int mmu_idx,
|
||||
unsigned int am, bool eu,
|
||||
target_ulong segmask,
|
||||
hwaddr physical_base)
|
||||
{
|
||||
int mapped = is_seg_am_mapped(am, eu, mmu_idx);
|
||||
|
||||
if (mapped < 0) {
|
||||
/* is_seg_am_mapped can report TLBRET_BADADDR */
|
||||
return mapped;
|
||||
} else if (mapped) {
|
||||
/* The segment is TLB mapped */
|
||||
return env->tlb->map_address(env, physical, prot, real_address,
|
||||
access_type);
|
||||
} else {
|
||||
/* The segment is unmapped */
|
||||
*physical = physical_base | (real_address & segmask);
|
||||
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
return TLBRET_MATCH;
|
||||
}
|
||||
}
|
||||
|
||||
static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
|
||||
int *prot, target_ulong real_address,
|
||||
MMUAccessType access_type, int mmu_idx,
|
||||
uint16_t segctl, target_ulong segmask)
|
||||
{
|
||||
unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM;
|
||||
bool eu = (segctl >> CP0SC_EU) & 1;
|
||||
hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20;
|
||||
|
||||
return get_seg_physical_address(env, physical, prot, real_address,
|
||||
access_type, mmu_idx, am, eu, segmask,
|
||||
pa & ~(hwaddr)segmask);
|
||||
}
|
||||
|
||||
int get_physical_address(CPUMIPSState *env, hwaddr *physical,
|
||||
int *prot, target_ulong real_address,
|
||||
MMUAccessType access_type, int mmu_idx)
|
||||
{
|
||||
/* User mode can only access useg/xuseg */
|
||||
#if defined(TARGET_MIPS64)
|
||||
int user_mode = mmu_idx == MIPS_HFLAG_UM;
|
||||
int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
|
||||
int kernel_mode = !user_mode && !supervisor_mode;
|
||||
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
|
||||
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
|
||||
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
|
||||
#endif
|
||||
int ret = TLBRET_MATCH;
|
||||
/* effective address (modified for KVM T&E kernel segments) */
|
||||
target_ulong address = real_address;
|
||||
|
||||
if (mips_um_ksegs_enabled()) {
|
||||
/* KVM T&E adds guest kernel segments in useg */
|
||||
if (real_address >= KVM_KSEG0_BASE) {
|
||||
if (real_address < KVM_KSEG2_BASE) {
|
||||
/* kseg0 */
|
||||
address += KSEG0_BASE - KVM_KSEG0_BASE;
|
||||
} else if (real_address <= USEG_LIMIT) {
|
||||
/* kseg2/3 */
|
||||
address += KSEG2_BASE - KVM_KSEG2_BASE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (address <= USEG_LIMIT) {
|
||||
/* useg */
|
||||
uint16_t segctl;
|
||||
|
||||
if (address >= 0x40000000UL) {
|
||||
segctl = env->CP0_SegCtl2;
|
||||
} else {
|
||||
segctl = env->CP0_SegCtl2 >> 16;
|
||||
}
|
||||
ret = get_segctl_physical_address(env, physical, prot,
|
||||
real_address, access_type,
|
||||
mmu_idx, segctl, 0x3FFFFFFF);
|
||||
#if defined(TARGET_MIPS64)
|
||||
} else if (address < 0x4000000000000000ULL) {
|
||||
/* xuseg */
|
||||
if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
|
||||
ret = env->tlb->map_address(env, physical, prot,
|
||||
real_address, access_type);
|
||||
} else {
|
||||
ret = TLBRET_BADADDR;
|
||||
}
|
||||
} else if (address < 0x8000000000000000ULL) {
|
||||
/* xsseg */
|
||||
if ((supervisor_mode || kernel_mode) &&
|
||||
SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
|
||||
ret = env->tlb->map_address(env, physical, prot,
|
||||
real_address, access_type);
|
||||
} else {
|
||||
ret = TLBRET_BADADDR;
|
||||
}
|
||||
} else if (address < 0xC000000000000000ULL) {
|
||||
/* xkphys */
|
||||
if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
|
||||
/* KX/SX/UX bit to check for each xkphys EVA access mode */
|
||||
static const uint8_t am_ksux[8] = {
|
||||
[CP0SC_AM_UK] = (1u << CP0St_KX),
|
||||
[CP0SC_AM_MK] = (1u << CP0St_KX),
|
||||
[CP0SC_AM_MSK] = (1u << CP0St_SX),
|
||||
[CP0SC_AM_MUSK] = (1u << CP0St_UX),
|
||||
[CP0SC_AM_MUSUK] = (1u << CP0St_UX),
|
||||
[CP0SC_AM_USK] = (1u << CP0St_SX),
|
||||
[6] = (1u << CP0St_KX),
|
||||
[CP0SC_AM_UUSK] = (1u << CP0St_UX),
|
||||
};
|
||||
unsigned int am = CP0SC_AM_UK;
|
||||
unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR;
|
||||
|
||||
if (xr & (1 << ((address >> 59) & 0x7))) {
|
||||
am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM;
|
||||
}
|
||||
/* Does CP0_Status.KX/SX/UX permit the access mode (am) */
|
||||
if (env->CP0_Status & am_ksux[am]) {
|
||||
ret = get_seg_physical_address(env, physical, prot,
|
||||
real_address, access_type,
|
||||
mmu_idx, am, false, env->PAMask,
|
||||
0);
|
||||
} else {
|
||||
ret = TLBRET_BADADDR;
|
||||
}
|
||||
} else {
|
||||
ret = TLBRET_BADADDR;
|
||||
}
|
||||
} else if (address < 0xFFFFFFFF80000000ULL) {
|
||||
/* xkseg */
|
||||
if (kernel_mode && KX &&
|
||||
address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
|
||||
ret = env->tlb->map_address(env, physical, prot,
|
||||
real_address, access_type);
|
||||
} else {
|
||||
ret = TLBRET_BADADDR;
|
||||
}
|
||||
#endif
|
||||
} else if (address < KSEG1_BASE) {
|
||||
/* kseg0 */
|
||||
ret = get_segctl_physical_address(env, physical, prot, real_address,
|
||||
access_type, mmu_idx,
|
||||
env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
|
||||
} else if (address < KSEG2_BASE) {
|
||||
/* kseg1 */
|
||||
ret = get_segctl_physical_address(env, physical, prot, real_address,
|
||||
access_type, mmu_idx,
|
||||
env->CP0_SegCtl1, 0x1FFFFFFF);
|
||||
} else if (address < KSEG3_BASE) {
|
||||
/* sseg (kseg2) */
|
||||
ret = get_segctl_physical_address(env, physical, prot, real_address,
|
||||
access_type, mmu_idx,
|
||||
env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
|
||||
} else {
|
||||
/*
|
||||
* kseg3
|
||||
* XXX: debug segment is not emulated
|
||||
*/
|
||||
ret = get_segctl_physical_address(env, physical, prot, real_address,
|
||||
access_type, mmu_idx,
|
||||
env->CP0_SegCtl0, 0x1FFFFFFF);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
hwaddr phys_addr;
|
||||
int prot;
|
||||
|
||||
if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
|
||||
cpu_mmu_index(env, false)) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return phys_addr;
|
||||
}
|
167
target/mips/tcg/exception.c
Normal file
167
target/mips/tcg/exception.c
Normal file
@ -0,0 +1,167 @@
|
||||
/*
|
||||
* MIPS Exceptions processing helpers for QEMU.
|
||||
*
|
||||
* Copyright (c) 2004-2005 Jocelyn Mayer
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "internal.h"
|
||||
#include "exec/helper-proto.h"
|
||||
#include "exec/exec-all.h"
|
||||
|
||||
target_ulong exception_resume_pc(CPUMIPSState *env)
|
||||
{
|
||||
target_ulong bad_pc;
|
||||
target_ulong isa_mode;
|
||||
|
||||
isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
|
||||
bad_pc = env->active_tc.PC | isa_mode;
|
||||
if (env->hflags & MIPS_HFLAG_BMASK) {
|
||||
/*
|
||||
* If the exception was raised from a delay slot, come back to
|
||||
* the jump.
|
||||
*/
|
||||
bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
|
||||
}
|
||||
|
||||
return bad_pc;
|
||||
}
|
||||
|
||||
void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
|
||||
int error_code)
|
||||
{
|
||||
do_raise_exception_err(env, exception, error_code, 0);
|
||||
}
|
||||
|
||||
void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
|
||||
{
|
||||
do_raise_exception(env, exception, GETPC());
|
||||
}
|
||||
|
||||
void helper_raise_exception_debug(CPUMIPSState *env)
|
||||
{
|
||||
do_raise_exception(env, EXCP_DEBUG, 0);
|
||||
}
|
||||
|
||||
static void raise_exception(CPUMIPSState *env, uint32_t exception)
|
||||
{
|
||||
do_raise_exception(env, exception, 0);
|
||||
}
|
||||
|
||||
void helper_wait(CPUMIPSState *env)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
|
||||
cs->halted = 1;
|
||||
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
|
||||
/*
|
||||
* Last instruction in the block, PC was updated before
|
||||
* - no need to recover PC and icount.
|
||||
*/
|
||||
raise_exception(env, EXCP_HLT);
|
||||
}
|
||||
|
||||
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
|
||||
env->active_tc.PC = tb->pc;
|
||||
env->hflags &= ~MIPS_HFLAG_BMASK;
|
||||
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
|
||||
}
|
||||
|
||||
bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
||||
{
|
||||
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
|
||||
if (cpu_mips_hw_interrupts_enabled(env) &&
|
||||
cpu_mips_hw_interrupts_pending(env)) {
|
||||
/* Raise it */
|
||||
cs->exception_index = EXCP_EXT_INTERRUPT;
|
||||
env->error_code = 0;
|
||||
mips_cpu_do_interrupt(cs);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static const char * const excp_names[EXCP_LAST + 1] = {
|
||||
[EXCP_RESET] = "reset",
|
||||
[EXCP_SRESET] = "soft reset",
|
||||
[EXCP_DSS] = "debug single step",
|
||||
[EXCP_DINT] = "debug interrupt",
|
||||
[EXCP_NMI] = "non-maskable interrupt",
|
||||
[EXCP_MCHECK] = "machine check",
|
||||
[EXCP_EXT_INTERRUPT] = "interrupt",
|
||||
[EXCP_DFWATCH] = "deferred watchpoint",
|
||||
[EXCP_DIB] = "debug instruction breakpoint",
|
||||
[EXCP_IWATCH] = "instruction fetch watchpoint",
|
||||
[EXCP_AdEL] = "address error load",
|
||||
[EXCP_AdES] = "address error store",
|
||||
[EXCP_TLBF] = "TLB refill",
|
||||
[EXCP_IBE] = "instruction bus error",
|
||||
[EXCP_DBp] = "debug breakpoint",
|
||||
[EXCP_SYSCALL] = "syscall",
|
||||
[EXCP_BREAK] = "break",
|
||||
[EXCP_CpU] = "coprocessor unusable",
|
||||
[EXCP_RI] = "reserved instruction",
|
||||
[EXCP_OVERFLOW] = "arithmetic overflow",
|
||||
[EXCP_TRAP] = "trap",
|
||||
[EXCP_FPE] = "floating point",
|
||||
[EXCP_DDBS] = "debug data break store",
|
||||
[EXCP_DWATCH] = "data watchpoint",
|
||||
[EXCP_LTLBL] = "TLB modify",
|
||||
[EXCP_TLBL] = "TLB load",
|
||||
[EXCP_TLBS] = "TLB store",
|
||||
[EXCP_DBE] = "data bus error",
|
||||
[EXCP_DDBL] = "debug data break load",
|
||||
[EXCP_THREAD] = "thread",
|
||||
[EXCP_MDMX] = "MDMX",
|
||||
[EXCP_C2E] = "precise coprocessor 2",
|
||||
[EXCP_CACHE] = "cache error",
|
||||
[EXCP_TLBXI] = "TLB execute-inhibit",
|
||||
[EXCP_TLBRI] = "TLB read-inhibit",
|
||||
[EXCP_MSADIS] = "MSA disabled",
|
||||
[EXCP_MSAFPE] = "MSA floating point",
|
||||
};
|
||||
|
||||
const char *mips_exception_name(int32_t exception)
|
||||
{
|
||||
if (exception < 0 || exception > EXCP_LAST) {
|
||||
return "unknown";
|
||||
}
|
||||
return excp_names[exception];
|
||||
}
|
||||
|
||||
void do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
|
||||
int error_code, uintptr_t pc)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
|
||||
qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
|
||||
__func__, exception, mips_exception_name(exception),
|
||||
error_code);
|
||||
cs->exception_index = exception;
|
||||
env->error_code = error_code;
|
||||
|
||||
cpu_loop_exit_restore(cs, pc);
|
||||
}
|
@ -38,14 +38,6 @@
|
||||
#define FP_TO_INT32_OVERFLOW 0x7fffffff
|
||||
#define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
|
||||
|
||||
/* convert MIPS rounding mode in FCR31 to IEEE library */
|
||||
const FloatRoundMode ieee_rm[4] = {
|
||||
float_round_nearest_even,
|
||||
float_round_to_zero,
|
||||
float_round_up,
|
||||
float_round_down
|
||||
};
|
||||
|
||||
target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
|
||||
{
|
||||
target_ulong arg1 = 0;
|
288
target/mips/tcg/ldst_helper.c
Normal file
288
target/mips/tcg/ldst_helper.c
Normal file
@ -0,0 +1,288 @@
|
||||
/*
|
||||
* MIPS emulation load/store helpers for QEMU.
|
||||
*
|
||||
* Copyright (c) 2004-2005 Jocelyn Mayer
|
||||
*
|
||||
* SPDX-License-Identifier: LGPL-2.1-or-later
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "exec/helper-proto.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "exec/memop.h"
|
||||
#include "internal.h"
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
|
||||
#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
|
||||
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
|
||||
{ \
|
||||
if (arg & almask) { \
|
||||
if (!(env->hflags & MIPS_HFLAG_DM)) { \
|
||||
env->CP0_BadVAddr = arg; \
|
||||
} \
|
||||
do_raise_exception(env, EXCP_AdEL, GETPC()); \
|
||||
} \
|
||||
env->CP0_LLAddr = cpu_mips_translate_address(env, arg, MMU_DATA_LOAD, \
|
||||
GETPC()); \
|
||||
env->lladdr = arg; \
|
||||
env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
|
||||
return env->llval; \
|
||||
}
|
||||
HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t))
|
||||
#ifdef TARGET_MIPS64
|
||||
HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
|
||||
#endif
|
||||
#undef HELPER_LD_ATOMIC
|
||||
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
#define GET_LMASK(v) ((v) & 3)
|
||||
#define GET_OFFSET(addr, offset) (addr + (offset))
|
||||
#else
|
||||
#define GET_LMASK(v) (((v) & 3) ^ 3)
|
||||
#define GET_OFFSET(addr, offset) (addr - (offset))
|
||||
#endif
|
||||
|
||||
void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
|
||||
int mem_idx)
|
||||
{
|
||||
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
|
||||
|
||||
if (GET_LMASK(arg2) <= 2) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK(arg2) <= 1) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK(arg2) == 0) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
}
|
||||
|
||||
void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
|
||||
int mem_idx)
|
||||
{
|
||||
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
|
||||
|
||||
if (GET_LMASK(arg2) >= 1) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK(arg2) >= 2) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK(arg2) == 3) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(TARGET_MIPS64)
|
||||
/*
|
||||
* "half" load and stores. We must do the memory access inline,
|
||||
* or fault handling won't work.
|
||||
*/
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
#define GET_LMASK64(v) ((v) & 7)
|
||||
#else
|
||||
#define GET_LMASK64(v) (((v) & 7) ^ 7)
|
||||
#endif
|
||||
|
||||
void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
|
||||
int mem_idx)
|
||||
{
|
||||
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
|
||||
|
||||
if (GET_LMASK64(arg2) <= 6) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) <= 5) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) <= 4) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) <= 3) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) <= 2) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) <= 1) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) <= 0) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1,
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
}
|
||||
|
||||
void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
|
||||
int mem_idx)
|
||||
{
|
||||
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
|
||||
|
||||
if (GET_LMASK64(arg2) >= 1) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) >= 2) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) >= 3) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) >= 4) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) >= 5) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) >= 6) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
|
||||
if (GET_LMASK64(arg2) == 7) {
|
||||
cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56),
|
||||
mem_idx, GETPC());
|
||||
}
|
||||
}
|
||||
#endif /* TARGET_MIPS64 */
|
||||
|
||||
static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
|
||||
|
||||
void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
||||
uint32_t mem_idx)
|
||||
{
|
||||
target_ulong base_reglist = reglist & 0xf;
|
||||
target_ulong do_r31 = reglist & 0x10;
|
||||
|
||||
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
|
||||
target_ulong i;
|
||||
|
||||
for (i = 0; i < base_reglist; i++) {
|
||||
env->active_tc.gpr[multiple_regs[i]] =
|
||||
(target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
|
||||
addr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
if (do_r31) {
|
||||
env->active_tc.gpr[31] =
|
||||
(target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
|
||||
}
|
||||
}
|
||||
|
||||
void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
||||
uint32_t mem_idx)
|
||||
{
|
||||
target_ulong base_reglist = reglist & 0xf;
|
||||
target_ulong do_r31 = reglist & 0x10;
|
||||
|
||||
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
|
||||
target_ulong i;
|
||||
|
||||
for (i = 0; i < base_reglist; i++) {
|
||||
cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
|
||||
mem_idx, GETPC());
|
||||
addr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
if (do_r31) {
|
||||
cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(TARGET_MIPS64)
|
||||
void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
||||
uint32_t mem_idx)
|
||||
{
|
||||
target_ulong base_reglist = reglist & 0xf;
|
||||
target_ulong do_r31 = reglist & 0x10;
|
||||
|
||||
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
|
||||
target_ulong i;
|
||||
|
||||
for (i = 0; i < base_reglist; i++) {
|
||||
env->active_tc.gpr[multiple_regs[i]] =
|
||||
cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
|
||||
addr += 8;
|
||||
}
|
||||
}
|
||||
|
||||
if (do_r31) {
|
||||
env->active_tc.gpr[31] =
|
||||
cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
|
||||
}
|
||||
}
|
||||
|
||||
void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
||||
uint32_t mem_idx)
|
||||
{
|
||||
target_ulong base_reglist = reglist & 0xf;
|
||||
target_ulong do_r31 = reglist & 0x10;
|
||||
|
||||
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
|
||||
target_ulong i;
|
||||
|
||||
for (i = 0; i < base_reglist; i++) {
|
||||
cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
|
||||
mem_idx, GETPC());
|
||||
addr += 8;
|
||||
}
|
||||
}
|
||||
|
||||
if (do_r31) {
|
||||
cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* TARGET_MIPS64 */
|
35
target/mips/tcg/meson.build
Normal file
35
target/mips/tcg/meson.build
Normal file
@ -0,0 +1,35 @@
|
||||
gen = [
|
||||
decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'),
|
||||
decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
|
||||
decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
|
||||
decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'),
|
||||
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
|
||||
]
|
||||
|
||||
mips_ss.add(gen)
|
||||
mips_ss.add(files(
|
||||
'dsp_helper.c',
|
||||
'exception.c',
|
||||
'fpu_helper.c',
|
||||
'ldst_helper.c',
|
||||
'lmmi_helper.c',
|
||||
'msa_helper.c',
|
||||
'msa_translate.c',
|
||||
'op_helper.c',
|
||||
'rel6_translate.c',
|
||||
'translate.c',
|
||||
'translate_addr_const.c',
|
||||
'txx9_translate.c',
|
||||
))
|
||||
mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
|
||||
'tx79_translate.c',
|
||||
), if_false: files(
|
||||
'mxu_translate.c',
|
||||
))
|
||||
|
||||
if have_user
|
||||
subdir('user')
|
||||
endif
|
||||
if have_system
|
||||
subdir('sysemu')
|
||||
endif
|
@ -8595,39 +8595,3 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
|
||||
cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
|
||||
#endif
|
||||
}
|
||||
|
||||
void msa_reset(CPUMIPSState *env)
|
||||
{
|
||||
if (!ase_msa_available(env)) {
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USER_ONLY
|
||||
/* MSA access enabled */
|
||||
env->CP0_Config5 |= 1 << CP0C5_MSAEn;
|
||||
env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MSA CSR:
|
||||
* - non-signaling floating point exception mode off (NX bit is 0)
|
||||
* - Cause, Enables, and Flags are all 0
|
||||
* - round to nearest / ties to even (RM bits are 0)
|
||||
*/
|
||||
env->active_tc.msacsr = 0;
|
||||
|
||||
restore_msa_fp_status(env);
|
||||
|
||||
/* tininess detected after rounding.*/
|
||||
set_float_detect_tininess(float_tininess_after_rounding,
|
||||
&env->active_tc.msa_fp_status);
|
||||
|
||||
/* clear float_status exception flags */
|
||||
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
|
||||
|
||||
/* clear float_status nan mode */
|
||||
set_default_nan_mode(0, &env->active_tc.msa_fp_status);
|
||||
|
||||
/* set proper signanling bit meaning ("1" means "quiet") */
|
||||
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
|
||||
}
|
420
target/mips/tcg/op_helper.c
Normal file
420
target/mips/tcg/op_helper.c
Normal file
@ -0,0 +1,420 @@
|
||||
/*
|
||||
* MIPS emulation helpers for qemu.
|
||||
*
|
||||
* Copyright (c) 2004-2005 Jocelyn Mayer
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "internal.h"
|
||||
#include "exec/helper-proto.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "exec/memop.h"
|
||||
#include "fpu_helper.h"
|
||||
|
||||
/* 64 bits arithmetic for 32 bits hosts */
|
||||
static inline uint64_t get_HILO(CPUMIPSState *env)
|
||||
{
|
||||
return ((uint64_t)(env->active_tc.HI[0]) << 32) |
|
||||
(uint32_t)env->active_tc.LO[0];
|
||||
}
|
||||
|
||||
static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
|
||||
{
|
||||
env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
|
||||
return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
|
||||
}
|
||||
|
||||
static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
|
||||
{
|
||||
target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
|
||||
env->active_tc.HI[0] = (int32_t)(HILO >> 32);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/* Multiplication variants of the vr54xx. */
|
||||
target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
|
||||
(int64_t)(int32_t)arg2));
|
||||
}
|
||||
|
||||
target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
|
||||
(uint64_t)(uint32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
|
||||
(int64_t)(int32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
|
||||
(int64_t)(int32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
|
||||
(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
|
||||
(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
|
||||
(int64_t)(int32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
|
||||
(int64_t)(int32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
|
||||
(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
|
||||
(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
|
||||
(uint64_t)(uint32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
|
||||
(int64_t)(int32_t)arg2);
|
||||
}
|
||||
|
||||
target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
|
||||
target_ulong arg2)
|
||||
{
|
||||
return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
|
||||
(uint64_t)(uint32_t)arg2);
|
||||
}
|
||||
|
||||
static inline target_ulong bitswap(target_ulong v)
|
||||
{
|
||||
v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
|
||||
((v & (target_ulong)0x5555555555555555ULL) << 1);
|
||||
v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
|
||||
((v & (target_ulong)0x3333333333333333ULL) << 2);
|
||||
v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
|
||||
((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
|
||||
return v;
|
||||
}
|
||||
|
||||
#ifdef TARGET_MIPS64
|
||||
target_ulong helper_dbitswap(target_ulong rt)
|
||||
{
|
||||
return bitswap(rt);
|
||||
}
|
||||
#endif
|
||||
|
||||
target_ulong helper_bitswap(target_ulong rt)
|
||||
{
|
||||
return (int32_t)bitswap(rt);
|
||||
}
|
||||
|
||||
target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
|
||||
uint32_t stripe)
|
||||
{
|
||||
int i;
|
||||
uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
|
||||
uint64_t tmp1 = tmp0;
|
||||
for (i = 0; i <= 46; i++) {
|
||||
int s;
|
||||
if (i & 0x8) {
|
||||
s = shift;
|
||||
} else {
|
||||
s = shiftx;
|
||||
}
|
||||
|
||||
if (stripe != 0 && !(i & 0x4)) {
|
||||
s = ~s;
|
||||
}
|
||||
if (s & 0x10) {
|
||||
if (tmp0 & (1LL << (i + 16))) {
|
||||
tmp1 |= 1LL << i;
|
||||
} else {
|
||||
tmp1 &= ~(1LL << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t tmp2 = tmp1;
|
||||
for (i = 0; i <= 38; i++) {
|
||||
int s;
|
||||
if (i & 0x4) {
|
||||
s = shift;
|
||||
} else {
|
||||
s = shiftx;
|
||||
}
|
||||
|
||||
if (s & 0x8) {
|
||||
if (tmp1 & (1LL << (i + 8))) {
|
||||
tmp2 |= 1LL << i;
|
||||
} else {
|
||||
tmp2 &= ~(1LL << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t tmp3 = tmp2;
|
||||
for (i = 0; i <= 34; i++) {
|
||||
int s;
|
||||
if (i & 0x2) {
|
||||
s = shift;
|
||||
} else {
|
||||
s = shiftx;
|
||||
}
|
||||
if (s & 0x4) {
|
||||
if (tmp2 & (1LL << (i + 4))) {
|
||||
tmp3 |= 1LL << i;
|
||||
} else {
|
||||
tmp3 &= ~(1LL << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t tmp4 = tmp3;
|
||||
for (i = 0; i <= 32; i++) {
|
||||
int s;
|
||||
if (i & 0x1) {
|
||||
s = shift;
|
||||
} else {
|
||||
s = shiftx;
|
||||
}
|
||||
if (s & 0x2) {
|
||||
if (tmp3 & (1LL << (i + 2))) {
|
||||
tmp4 |= 1LL << i;
|
||||
} else {
|
||||
tmp4 &= ~(1LL << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t tmp5 = tmp4;
|
||||
for (i = 0; i <= 31; i++) {
|
||||
int s;
|
||||
s = shift;
|
||||
if (s & 0x1) {
|
||||
if (tmp4 & (1LL << (i + 1))) {
|
||||
tmp5 |= 1LL << i;
|
||||
} else {
|
||||
tmp5 &= ~(1LL << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (int64_t)(int32_t)(uint32_t)tmp5;
|
||||
}
|
||||
|
||||
void helper_fork(target_ulong arg1, target_ulong arg2)
|
||||
{
|
||||
/*
|
||||
* arg1 = rt, arg2 = rs
|
||||
* TODO: store to TC register
|
||||
*/
|
||||
}
|
||||
|
||||
target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
|
||||
{
|
||||
target_long arg1 = arg;
|
||||
|
||||
if (arg1 < 0) {
|
||||
/* No scheduling policy implemented. */
|
||||
if (arg1 != -2) {
|
||||
if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
|
||||
env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
|
||||
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
||||
env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
|
||||
do_raise_exception(env, EXCP_THREAD, GETPC());
|
||||
}
|
||||
}
|
||||
} else if (arg1 == 0) {
|
||||
if (0) {
|
||||
/* TODO: TC underflow */
|
||||
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
||||
do_raise_exception(env, EXCP_THREAD, GETPC());
|
||||
} else {
|
||||
/* TODO: Deallocate TC */
|
||||
}
|
||||
} else if (arg1 > 0) {
|
||||
/* Yield qualifier inputs not implemented. */
|
||||
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
||||
env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
|
||||
do_raise_exception(env, EXCP_THREAD, GETPC());
|
||||
}
|
||||
return env->CP0_YQMask;
|
||||
}
|
||||
|
||||
static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
|
||||
{
|
||||
if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
|
||||
return;
|
||||
}
|
||||
do_raise_exception(env, EXCP_RI, pc);
|
||||
}
|
||||
|
||||
target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
|
||||
{
|
||||
check_hwrena(env, 0, GETPC());
|
||||
return env->CP0_EBase & 0x3ff;
|
||||
}
|
||||
|
||||
target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
|
||||
{
|
||||
check_hwrena(env, 1, GETPC());
|
||||
return env->SYNCI_Step;
|
||||
}
|
||||
|
||||
target_ulong helper_rdhwr_cc(CPUMIPSState *env)
|
||||
{
|
||||
check_hwrena(env, 2, GETPC());
|
||||
#ifdef CONFIG_USER_ONLY
|
||||
return env->CP0_Count;
|
||||
#else
|
||||
return (int32_t)cpu_mips_get_count(env);
|
||||
#endif
|
||||
}
|
||||
|
||||
target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
|
||||
{
|
||||
check_hwrena(env, 3, GETPC());
|
||||
return env->CCRes;
|
||||
}
|
||||
|
||||
target_ulong helper_rdhwr_performance(CPUMIPSState *env)
|
||||
{
|
||||
check_hwrena(env, 4, GETPC());
|
||||
return env->CP0_Performance0;
|
||||
}
|
||||
|
||||
target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
|
||||
{
|
||||
check_hwrena(env, 5, GETPC());
|
||||
return (env->CP0_Config5 >> CP0C5_XNP) & 1;
|
||||
}
|
||||
|
||||
void helper_pmon(CPUMIPSState *env, int function)
|
||||
{
|
||||
function /= 2;
|
||||
switch (function) {
|
||||
case 2: /* TODO: char inbyte(int waitflag); */
|
||||
if (env->active_tc.gpr[4] == 0) {
|
||||
env->active_tc.gpr[2] = -1;
|
||||
}
|
||||
/* Fall through */
|
||||
case 11: /* TODO: char inbyte (void); */
|
||||
env->active_tc.gpr[2] = -1;
|
||||
break;
|
||||
case 3:
|
||||
case 12:
|
||||
printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
|
||||
break;
|
||||
case 17:
|
||||
break;
|
||||
case 158:
|
||||
{
|
||||
unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
|
||||
printf("%s", fmt);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
|
||||
MMUAccessType access_type,
|
||||
int mmu_idx, uintptr_t retaddr)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
int error_code = 0;
|
||||
int excp;
|
||||
|
||||
if (!(env->hflags & MIPS_HFLAG_DM)) {
|
||||
env->CP0_BadVAddr = addr;
|
||||
}
|
||||
|
||||
if (access_type == MMU_DATA_STORE) {
|
||||
excp = EXCP_AdES;
|
||||
} else {
|
||||
excp = EXCP_AdEL;
|
||||
if (access_type == MMU_INST_FETCH) {
|
||||
error_code |= EXCP_INST_NOTAVAIL;
|
||||
}
|
||||
}
|
||||
|
||||
do_raise_exception_err(env, excp, error_code, retaddr);
|
||||
}
|
||||
|
||||
void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
|
||||
vaddr addr, unsigned size,
|
||||
MMUAccessType access_type,
|
||||
int mmu_idx, MemTxAttrs attrs,
|
||||
MemTxResult response, uintptr_t retaddr)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
|
||||
if (access_type == MMU_INST_FETCH) {
|
||||
do_raise_exception(env, EXCP_IBE, retaddr);
|
||||
} else {
|
||||
do_raise_exception(env, EXCP_DBE, retaddr);
|
||||
}
|
||||
}
|
||||
#endif /* !CONFIG_USER_ONLY */
|
6
target/mips/tcg/sysemu/meson.build
Normal file
6
target/mips/tcg/sysemu/meson.build
Normal file
@ -0,0 +1,6 @@
|
||||
mips_softmmu_ss.add(files(
|
||||
'cp0_helper.c',
|
||||
'mips-semi.c',
|
||||
'special_helper.c',
|
||||
'tlb_helper.c',
|
||||
))
|
173
target/mips/tcg/sysemu/special_helper.c
Normal file
173
target/mips/tcg/sysemu/special_helper.c
Normal file
@ -0,0 +1,173 @@
|
||||
/*
|
||||
* QEMU MIPS emulation: Special opcode helpers
|
||||
*
|
||||
* Copyright (c) 2004-2005 Jocelyn Mayer
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "exec/helper-proto.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "internal.h"
|
||||
|
||||
/* Specials */
|
||||
target_ulong helper_di(CPUMIPSState *env)
|
||||
{
|
||||
target_ulong t0 = env->CP0_Status;
|
||||
|
||||
env->CP0_Status = t0 & ~(1 << CP0St_IE);
|
||||
return t0;
|
||||
}
|
||||
|
||||
target_ulong helper_ei(CPUMIPSState *env)
|
||||
{
|
||||
target_ulong t0 = env->CP0_Status;
|
||||
|
||||
env->CP0_Status = t0 | (1 << CP0St_IE);
|
||||
return t0;
|
||||
}
|
||||
|
||||
static void debug_pre_eret(CPUMIPSState *env)
|
||||
{
|
||||
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
||||
qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
|
||||
env->active_tc.PC, env->CP0_EPC);
|
||||
if (env->CP0_Status & (1 << CP0St_ERL)) {
|
||||
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
||||
}
|
||||
if (env->hflags & MIPS_HFLAG_DM) {
|
||||
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
||||
}
|
||||
qemu_log("\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void debug_post_eret(CPUMIPSState *env)
|
||||
{
|
||||
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
||||
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
|
||||
env->active_tc.PC, env->CP0_EPC);
|
||||
if (env->CP0_Status & (1 << CP0St_ERL)) {
|
||||
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
||||
}
|
||||
if (env->hflags & MIPS_HFLAG_DM) {
|
||||
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
||||
}
|
||||
switch (cpu_mmu_index(env, false)) {
|
||||
case 3:
|
||||
qemu_log(", ERL\n");
|
||||
break;
|
||||
case MIPS_HFLAG_UM:
|
||||
qemu_log(", UM\n");
|
||||
break;
|
||||
case MIPS_HFLAG_SM:
|
||||
qemu_log(", SM\n");
|
||||
break;
|
||||
case MIPS_HFLAG_KM:
|
||||
qemu_log("\n");
|
||||
break;
|
||||
default:
|
||||
cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
|
||||
if ((env->hflags & MIPS_HFLAG_BMASK) != 0
|
||||
&& env->active_tc.PC != tb->pc) {
|
||||
env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
|
||||
env->hflags &= ~MIPS_HFLAG_BMASK;
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline void exception_return(CPUMIPSState *env)
|
||||
{
|
||||
debug_pre_eret(env);
|
||||
if (env->CP0_Status & (1 << CP0St_ERL)) {
|
||||
mips_env_set_pc(env, env->CP0_ErrorEPC);
|
||||
env->CP0_Status &= ~(1 << CP0St_ERL);
|
||||
} else {
|
||||
mips_env_set_pc(env, env->CP0_EPC);
|
||||
env->CP0_Status &= ~(1 << CP0St_EXL);
|
||||
}
|
||||
compute_hflags(env);
|
||||
debug_post_eret(env);
|
||||
}
|
||||
|
||||
void helper_eret(CPUMIPSState *env)
|
||||
{
|
||||
exception_return(env);
|
||||
env->CP0_LLAddr = 1;
|
||||
env->lladdr = 1;
|
||||
}
|
||||
|
||||
void helper_eretnc(CPUMIPSState *env)
|
||||
{
|
||||
exception_return(env);
|
||||
}
|
||||
|
||||
void helper_deret(CPUMIPSState *env)
|
||||
{
|
||||
debug_pre_eret(env);
|
||||
|
||||
env->hflags &= ~MIPS_HFLAG_DM;
|
||||
compute_hflags(env);
|
||||
|
||||
mips_env_set_pc(env, env->CP0_DEPC);
|
||||
|
||||
debug_post_eret(env);
|
||||
}
|
||||
|
||||
void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
|
||||
{
|
||||
static const char *const type_name[] = {
|
||||
"Primary Instruction",
|
||||
"Primary Data or Unified Primary",
|
||||
"Tertiary",
|
||||
"Secondary"
|
||||
};
|
||||
uint32_t cache_type = extract32(op, 0, 2);
|
||||
uint32_t cache_operation = extract32(op, 2, 3);
|
||||
target_ulong index = addr & 0x1fffffff;
|
||||
|
||||
switch (cache_operation) {
|
||||
case 0b010: /* Index Store Tag */
|
||||
memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
|
||||
MO_64, MEMTXATTRS_UNSPECIFIED);
|
||||
break;
|
||||
case 0b001: /* Index Load Tag */
|
||||
memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
|
||||
MO_64, MEMTXATTRS_UNSPECIFIED);
|
||||
break;
|
||||
case 0b000: /* Index Invalidate */
|
||||
case 0b100: /* Hit Invalidate */
|
||||
case 0b110: /* Hit Writeback */
|
||||
/* no-op */
|
||||
break;
|
||||
default:
|
||||
qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n",
|
||||
cache_operation, type_name[cache_type]);
|
||||
break;
|
||||
}
|
||||
}
|
@ -24,22 +24,341 @@
|
||||
#include "exec/cpu_ldst.h"
|
||||
#include "exec/log.h"
|
||||
#include "hw/mips/cpudevs.h"
|
||||
#include "exec/helper-proto.h"
|
||||
|
||||
enum {
|
||||
TLBRET_XI = -6,
|
||||
TLBRET_RI = -5,
|
||||
TLBRET_DIRTY = -4,
|
||||
TLBRET_INVALID = -3,
|
||||
TLBRET_NOMATCH = -2,
|
||||
TLBRET_BADADDR = -1,
|
||||
TLBRET_MATCH = 0
|
||||
};
|
||||
/* TLB management */
|
||||
static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first)
|
||||
{
|
||||
/* Discard entries from env->tlb[first] onwards. */
|
||||
while (env->tlb->tlb_in_use > first) {
|
||||
r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
|
||||
}
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
|
||||
{
|
||||
#if defined(TARGET_MIPS64)
|
||||
return extract64(entrylo, 6, 54);
|
||||
#else
|
||||
return extract64(entrylo, 6, 24) | /* PFN */
|
||||
(extract64(entrylo, 32, 32) << 24); /* PFNX */
|
||||
#endif
|
||||
}
|
||||
|
||||
static void r4k_fill_tlb(CPUMIPSState *env, int idx)
|
||||
{
|
||||
r4k_tlb_t *tlb;
|
||||
uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
|
||||
|
||||
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
||||
tlb = &env->tlb->mmu.r4k.tlb[idx];
|
||||
if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
|
||||
tlb->EHINV = 1;
|
||||
return;
|
||||
}
|
||||
tlb->EHINV = 0;
|
||||
tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
||||
#if defined(TARGET_MIPS64)
|
||||
tlb->VPN &= env->SEGMask;
|
||||
#endif
|
||||
tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
|
||||
tlb->MMID = env->CP0_MemoryMapID;
|
||||
tlb->PageMask = env->CP0_PageMask;
|
||||
tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
||||
tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
|
||||
tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
|
||||
tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
|
||||
tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
|
||||
tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
|
||||
tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
|
||||
tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
|
||||
tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
|
||||
tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
|
||||
tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
|
||||
tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
|
||||
tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
|
||||
}
|
||||
|
||||
static void r4k_helper_tlbinv(CPUMIPSState *env)
|
||||
{
|
||||
bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
|
||||
uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
|
||||
uint32_t MMID = env->CP0_MemoryMapID;
|
||||
uint32_t tlb_mmid;
|
||||
r4k_tlb_t *tlb;
|
||||
int idx;
|
||||
|
||||
MMID = mi ? MMID : (uint32_t) ASID;
|
||||
for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
|
||||
tlb = &env->tlb->mmu.r4k.tlb[idx];
|
||||
tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
|
||||
if (!tlb->G && tlb_mmid == MMID) {
|
||||
tlb->EHINV = 1;
|
||||
}
|
||||
}
|
||||
cpu_mips_tlb_flush(env);
|
||||
}
|
||||
|
||||
static void r4k_helper_tlbinvf(CPUMIPSState *env)
|
||||
{
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
|
||||
env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
|
||||
}
|
||||
cpu_mips_tlb_flush(env);
|
||||
}
|
||||
|
||||
static void r4k_helper_tlbwi(CPUMIPSState *env)
|
||||
{
|
||||
bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
|
||||
target_ulong VPN;
|
||||
uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
|
||||
uint32_t MMID = env->CP0_MemoryMapID;
|
||||
uint32_t tlb_mmid;
|
||||
bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1;
|
||||
r4k_tlb_t *tlb;
|
||||
int idx;
|
||||
|
||||
MMID = mi ? MMID : (uint32_t) ASID;
|
||||
|
||||
idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
|
||||
tlb = &env->tlb->mmu.r4k.tlb[idx];
|
||||
VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
||||
#if defined(TARGET_MIPS64)
|
||||
VPN &= env->SEGMask;
|
||||
#endif
|
||||
EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0;
|
||||
G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
||||
V0 = (env->CP0_EntryLo0 & 2) != 0;
|
||||
D0 = (env->CP0_EntryLo0 & 4) != 0;
|
||||
XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1;
|
||||
RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1;
|
||||
V1 = (env->CP0_EntryLo1 & 2) != 0;
|
||||
D1 = (env->CP0_EntryLo1 & 4) != 0;
|
||||
XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
|
||||
RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
|
||||
|
||||
tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
|
||||
/*
|
||||
* Discard cached TLB entries, unless tlbwi is just upgrading access
|
||||
* permissions on the current entry.
|
||||
*/
|
||||
if (tlb->VPN != VPN || tlb_mmid != MMID || tlb->G != G ||
|
||||
(!tlb->EHINV && EHINV) ||
|
||||
(tlb->V0 && !V0) || (tlb->D0 && !D0) ||
|
||||
(!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) ||
|
||||
(tlb->V1 && !V1) || (tlb->D1 && !D1) ||
|
||||
(!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) {
|
||||
r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
|
||||
}
|
||||
|
||||
r4k_invalidate_tlb(env, idx, 0);
|
||||
r4k_fill_tlb(env, idx);
|
||||
}
|
||||
|
||||
static void r4k_helper_tlbwr(CPUMIPSState *env)
|
||||
{
|
||||
int r = cpu_mips_get_random(env);
|
||||
|
||||
r4k_invalidate_tlb(env, r, 1);
|
||||
r4k_fill_tlb(env, r);
|
||||
}
|
||||
|
||||
static void r4k_helper_tlbp(CPUMIPSState *env)
|
||||
{
|
||||
bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
|
||||
r4k_tlb_t *tlb;
|
||||
target_ulong mask;
|
||||
target_ulong tag;
|
||||
target_ulong VPN;
|
||||
uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
|
||||
uint32_t MMID = env->CP0_MemoryMapID;
|
||||
uint32_t tlb_mmid;
|
||||
int i;
|
||||
|
||||
MMID = mi ? MMID : (uint32_t) ASID;
|
||||
for (i = 0; i < env->tlb->nb_tlb; i++) {
|
||||
tlb = &env->tlb->mmu.r4k.tlb[i];
|
||||
/* 1k pages are not supported. */
|
||||
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
||||
tag = env->CP0_EntryHi & ~mask;
|
||||
VPN = tlb->VPN & ~mask;
|
||||
#if defined(TARGET_MIPS64)
|
||||
tag &= env->SEGMask;
|
||||
#endif
|
||||
tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
|
||||
/* Check ASID/MMID, virtual page number & size */
|
||||
if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) {
|
||||
/* TLB match */
|
||||
env->CP0_Index = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (i == env->tlb->nb_tlb) {
|
||||
/* No match. Discard any shadow entries, if any of them match. */
|
||||
for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
|
||||
tlb = &env->tlb->mmu.r4k.tlb[i];
|
||||
/* 1k pages are not supported. */
|
||||
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
||||
tag = env->CP0_EntryHi & ~mask;
|
||||
VPN = tlb->VPN & ~mask;
|
||||
#if defined(TARGET_MIPS64)
|
||||
tag &= env->SEGMask;
|
||||
#endif
|
||||
tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
|
||||
/* Check ASID/MMID, virtual page number & size */
|
||||
if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag) {
|
||||
r4k_mips_tlb_flush_extra(env, i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
env->CP0_Index |= 0x80000000;
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
|
||||
{
|
||||
#if defined(TARGET_MIPS64)
|
||||
return tlb_pfn << 6;
|
||||
#else
|
||||
return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
|
||||
(extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
|
||||
#endif
|
||||
}
|
||||
|
||||
static void r4k_helper_tlbr(CPUMIPSState *env)
|
||||
{
|
||||
bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
|
||||
uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
|
||||
uint32_t MMID = env->CP0_MemoryMapID;
|
||||
uint32_t tlb_mmid;
|
||||
r4k_tlb_t *tlb;
|
||||
int idx;
|
||||
|
||||
MMID = mi ? MMID : (uint32_t) ASID;
|
||||
idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
|
||||
tlb = &env->tlb->mmu.r4k.tlb[idx];
|
||||
|
||||
tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
|
||||
/* If this will change the current ASID/MMID, flush qemu's TLB. */
|
||||
if (MMID != tlb_mmid) {
|
||||
cpu_mips_tlb_flush(env);
|
||||
}
|
||||
|
||||
r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
|
||||
|
||||
if (tlb->EHINV) {
|
||||
env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
|
||||
env->CP0_PageMask = 0;
|
||||
env->CP0_EntryLo0 = 0;
|
||||
env->CP0_EntryLo1 = 0;
|
||||
} else {
|
||||
env->CP0_EntryHi = mi ? tlb->VPN : tlb->VPN | tlb->ASID;
|
||||
env->CP0_MemoryMapID = tlb->MMID;
|
||||
env->CP0_PageMask = tlb->PageMask;
|
||||
env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
|
||||
((uint64_t)tlb->RI0 << CP0EnLo_RI) |
|
||||
((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
|
||||
get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
|
||||
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
|
||||
((uint64_t)tlb->RI1 << CP0EnLo_RI) |
|
||||
((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
|
||||
get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
|
||||
}
|
||||
}
|
||||
|
||||
void helper_tlbwi(CPUMIPSState *env)
|
||||
{
|
||||
env->tlb->helper_tlbwi(env);
|
||||
}
|
||||
|
||||
void helper_tlbwr(CPUMIPSState *env)
|
||||
{
|
||||
env->tlb->helper_tlbwr(env);
|
||||
}
|
||||
|
||||
void helper_tlbp(CPUMIPSState *env)
|
||||
{
|
||||
env->tlb->helper_tlbp(env);
|
||||
}
|
||||
|
||||
void helper_tlbr(CPUMIPSState *env)
|
||||
{
|
||||
env->tlb->helper_tlbr(env);
|
||||
}
|
||||
|
||||
void helper_tlbinv(CPUMIPSState *env)
|
||||
{
|
||||
env->tlb->helper_tlbinv(env);
|
||||
}
|
||||
|
||||
void helper_tlbinvf(CPUMIPSState *env)
|
||||
{
|
||||
env->tlb->helper_tlbinvf(env);
|
||||
}
|
||||
|
||||
static void global_invalidate_tlb(CPUMIPSState *env,
|
||||
uint32_t invMsgVPN2,
|
||||
uint8_t invMsgR,
|
||||
uint32_t invMsgMMid,
|
||||
bool invAll,
|
||||
bool invVAMMid,
|
||||
bool invMMid,
|
||||
bool invVA)
|
||||
{
|
||||
|
||||
int idx;
|
||||
r4k_tlb_t *tlb;
|
||||
bool VAMatch;
|
||||
bool MMidMatch;
|
||||
|
||||
for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
|
||||
tlb = &env->tlb->mmu.r4k.tlb[idx];
|
||||
VAMatch =
|
||||
(((tlb->VPN & ~tlb->PageMask) == (invMsgVPN2 & ~tlb->PageMask))
|
||||
#ifdef TARGET_MIPS64
|
||||
&&
|
||||
(extract64(env->CP0_EntryHi, 62, 2) == invMsgR)
|
||||
#endif
|
||||
);
|
||||
MMidMatch = tlb->MMID == invMsgMMid;
|
||||
if ((invAll && (idx > env->CP0_Wired)) ||
|
||||
(VAMatch && invVAMMid && (tlb->G || MMidMatch)) ||
|
||||
(VAMatch && invVA) ||
|
||||
(MMidMatch && !(tlb->G) && invMMid)) {
|
||||
tlb->EHINV = 1;
|
||||
}
|
||||
}
|
||||
cpu_mips_tlb_flush(env);
|
||||
}
|
||||
|
||||
void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type)
|
||||
{
|
||||
bool invAll = type == 0;
|
||||
bool invVA = type == 1;
|
||||
bool invMMid = type == 2;
|
||||
bool invVAMMid = type == 3;
|
||||
uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1);
|
||||
uint8_t invMsgR = 0;
|
||||
uint32_t invMsgMMid = env->CP0_MemoryMapID;
|
||||
CPUState *other_cs = first_cpu;
|
||||
|
||||
#ifdef TARGET_MIPS64
|
||||
invMsgR = extract64(arg, 62, 2);
|
||||
#endif
|
||||
|
||||
CPU_FOREACH(other_cs) {
|
||||
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
|
||||
global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsgMMid,
|
||||
invAll, invVAMMid, invMMid, invVA);
|
||||
}
|
||||
}
|
||||
|
||||
/* no MMU emulation */
|
||||
int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
|
||||
target_ulong address, MMUAccessType access_type)
|
||||
static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
|
||||
target_ulong address, MMUAccessType access_type)
|
||||
{
|
||||
*physical = address;
|
||||
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
@ -47,8 +366,9 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
|
||||
}
|
||||
|
||||
/* fixed mapping MMU emulation */
|
||||
int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
|
||||
target_ulong address, MMUAccessType access_type)
|
||||
static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical,
|
||||
int *prot, target_ulong address,
|
||||
MMUAccessType access_type)
|
||||
{
|
||||
if (address <= (int32_t)0x7FFFFFFFUL) {
|
||||
if (!(env->CP0_Status & (1 << CP0St_ERL))) {
|
||||
@ -67,8 +387,8 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
|
||||
}
|
||||
|
||||
/* MIPS32/MIPS64 R4000-style MMU emulation */
|
||||
int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
|
||||
target_ulong address, MMUAccessType access_type)
|
||||
static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
|
||||
target_ulong address, MMUAccessType access_type)
|
||||
{
|
||||
uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
|
||||
uint32_t MMID = env->CP0_MemoryMapID;
|
||||
@ -166,236 +486,6 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *def)
|
||||
}
|
||||
}
|
||||
|
||||
static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
|
||||
{
|
||||
/*
|
||||
* Interpret access control mode and mmu_idx.
|
||||
* AdE? TLB?
|
||||
* AM K S U E K S U E
|
||||
* UK 0 0 1 1 0 0 - - 0
|
||||
* MK 1 0 1 1 0 1 - - !eu
|
||||
* MSK 2 0 0 1 0 1 1 - !eu
|
||||
* MUSK 3 0 0 0 0 1 1 1 !eu
|
||||
* MUSUK 4 0 0 0 0 0 1 1 0
|
||||
* USK 5 0 0 1 0 0 0 - 0
|
||||
* - 6 - - - - - - - -
|
||||
* UUSK 7 0 0 0 0 0 0 0 0
|
||||
*/
|
||||
int32_t adetlb_mask;
|
||||
|
||||
switch (mmu_idx) {
|
||||
case 3: /* ERL */
|
||||
/* If EU is set, always unmapped */
|
||||
if (eu) {
|
||||
return 0;
|
||||
}
|
||||
/* fall through */
|
||||
case MIPS_HFLAG_KM:
|
||||
/* Never AdE, TLB mapped if AM={1,2,3} */
|
||||
adetlb_mask = 0x70000000;
|
||||
goto check_tlb;
|
||||
|
||||
case MIPS_HFLAG_SM:
|
||||
/* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
|
||||
adetlb_mask = 0xc0380000;
|
||||
goto check_ade;
|
||||
|
||||
case MIPS_HFLAG_UM:
|
||||
/* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
|
||||
adetlb_mask = 0xe4180000;
|
||||
/* fall through */
|
||||
check_ade:
|
||||
/* does this AM cause AdE in current execution mode */
|
||||
if ((adetlb_mask << am) < 0) {
|
||||
return TLBRET_BADADDR;
|
||||
}
|
||||
adetlb_mask <<= 8;
|
||||
/* fall through */
|
||||
check_tlb:
|
||||
/* is this AM mapped in current execution mode */
|
||||
return ((adetlb_mask << am) < 0);
|
||||
default:
|
||||
assert(0);
|
||||
return TLBRET_BADADDR;
|
||||
};
|
||||
}
|
||||
|
||||
static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
|
||||
int *prot, target_ulong real_address,
|
||||
MMUAccessType access_type, int mmu_idx,
|
||||
unsigned int am, bool eu,
|
||||
target_ulong segmask,
|
||||
hwaddr physical_base)
|
||||
{
|
||||
int mapped = is_seg_am_mapped(am, eu, mmu_idx);
|
||||
|
||||
if (mapped < 0) {
|
||||
/* is_seg_am_mapped can report TLBRET_BADADDR */
|
||||
return mapped;
|
||||
} else if (mapped) {
|
||||
/* The segment is TLB mapped */
|
||||
return env->tlb->map_address(env, physical, prot, real_address,
|
||||
access_type);
|
||||
} else {
|
||||
/* The segment is unmapped */
|
||||
*physical = physical_base | (real_address & segmask);
|
||||
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
return TLBRET_MATCH;
|
||||
}
|
||||
}
|
||||
|
||||
static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
|
||||
int *prot, target_ulong real_address,
|
||||
MMUAccessType access_type, int mmu_idx,
|
||||
uint16_t segctl, target_ulong segmask)
|
||||
{
|
||||
unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM;
|
||||
bool eu = (segctl >> CP0SC_EU) & 1;
|
||||
hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20;
|
||||
|
||||
return get_seg_physical_address(env, physical, prot, real_address,
|
||||
access_type, mmu_idx, am, eu, segmask,
|
||||
pa & ~(hwaddr)segmask);
|
||||
}
|
||||
|
||||
static int get_physical_address(CPUMIPSState *env, hwaddr *physical,
|
||||
int *prot, target_ulong real_address,
|
||||
MMUAccessType access_type, int mmu_idx)
|
||||
{
|
||||
/* User mode can only access useg/xuseg */
|
||||
#if defined(TARGET_MIPS64)
|
||||
int user_mode = mmu_idx == MIPS_HFLAG_UM;
|
||||
int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
|
||||
int kernel_mode = !user_mode && !supervisor_mode;
|
||||
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
|
||||
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
|
||||
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
|
||||
#endif
|
||||
int ret = TLBRET_MATCH;
|
||||
/* effective address (modified for KVM T&E kernel segments) */
|
||||
target_ulong address = real_address;
|
||||
|
||||
#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
|
||||
#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
|
||||
#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
|
||||
#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
|
||||
#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
|
||||
|
||||
#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
|
||||
#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
|
||||
|
||||
if (mips_um_ksegs_enabled()) {
|
||||
/* KVM T&E adds guest kernel segments in useg */
|
||||
if (real_address >= KVM_KSEG0_BASE) {
|
||||
if (real_address < KVM_KSEG2_BASE) {
|
||||
/* kseg0 */
|
||||
address += KSEG0_BASE - KVM_KSEG0_BASE;
|
||||
} else if (real_address <= USEG_LIMIT) {
|
||||
/* kseg2/3 */
|
||||
address += KSEG2_BASE - KVM_KSEG2_BASE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (address <= USEG_LIMIT) {
|
||||
/* useg */
|
||||
uint16_t segctl;
|
||||
|
||||
if (address >= 0x40000000UL) {
|
||||
segctl = env->CP0_SegCtl2;
|
||||
} else {
|
||||
segctl = env->CP0_SegCtl2 >> 16;
|
||||
}
|
||||
ret = get_segctl_physical_address(env, physical, prot,
|
||||
real_address, access_type,
|
||||
mmu_idx, segctl, 0x3FFFFFFF);
|
||||
#if defined(TARGET_MIPS64)
|
||||
} else if (address < 0x4000000000000000ULL) {
|
||||
/* xuseg */
|
||||
if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
|
||||
ret = env->tlb->map_address(env, physical, prot,
|
||||
real_address, access_type);
|
||||
} else {
|
||||
ret = TLBRET_BADADDR;
|
||||
}
|
||||
} else if (address < 0x8000000000000000ULL) {
|
||||
/* xsseg */
|
||||
if ((supervisor_mode || kernel_mode) &&
|
||||
SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
|
||||
ret = env->tlb->map_address(env, physical, prot,
|
||||
real_address, access_type);
|
||||
} else {
|
||||
ret = TLBRET_BADADDR;
|
||||
}
|
||||
} else if (address < 0xC000000000000000ULL) {
|
||||
/* xkphys */
|
||||
if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
|
||||
/* KX/SX/UX bit to check for each xkphys EVA access mode */
|
||||
static const uint8_t am_ksux[8] = {
|
||||
[CP0SC_AM_UK] = (1u << CP0St_KX),
|
||||
[CP0SC_AM_MK] = (1u << CP0St_KX),
|
||||
[CP0SC_AM_MSK] = (1u << CP0St_SX),
|
||||
[CP0SC_AM_MUSK] = (1u << CP0St_UX),
|
||||
[CP0SC_AM_MUSUK] = (1u << CP0St_UX),
|
||||
[CP0SC_AM_USK] = (1u << CP0St_SX),
|
||||
[6] = (1u << CP0St_KX),
|
||||
[CP0SC_AM_UUSK] = (1u << CP0St_UX),
|
||||
};
|
||||
unsigned int am = CP0SC_AM_UK;
|
||||
unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR;
|
||||
|
||||
if (xr & (1 << ((address >> 59) & 0x7))) {
|
||||
am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM;
|
||||
}
|
||||
/* Does CP0_Status.KX/SX/UX permit the access mode (am) */
|
||||
if (env->CP0_Status & am_ksux[am]) {
|
||||
ret = get_seg_physical_address(env, physical, prot,
|
||||
real_address, access_type,
|
||||
mmu_idx, am, false, env->PAMask,
|
||||
0);
|
||||
} else {
|
||||
ret = TLBRET_BADADDR;
|
||||
}
|
||||
} else {
|
||||
ret = TLBRET_BADADDR;
|
||||
}
|
||||
} else if (address < 0xFFFFFFFF80000000ULL) {
|
||||
/* xkseg */
|
||||
if (kernel_mode && KX &&
|
||||
address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
|
||||
ret = env->tlb->map_address(env, physical, prot,
|
||||
real_address, access_type);
|
||||
} else {
|
||||
ret = TLBRET_BADADDR;
|
||||
}
|
||||
#endif
|
||||
} else if (address < KSEG1_BASE) {
|
||||
/* kseg0 */
|
||||
ret = get_segctl_physical_address(env, physical, prot, real_address,
|
||||
access_type, mmu_idx,
|
||||
env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
|
||||
} else if (address < KSEG2_BASE) {
|
||||
/* kseg1 */
|
||||
ret = get_segctl_physical_address(env, physical, prot, real_address,
|
||||
access_type, mmu_idx,
|
||||
env->CP0_SegCtl1, 0x1FFFFFFF);
|
||||
} else if (address < KSEG3_BASE) {
|
||||
/* sseg (kseg2) */
|
||||
ret = get_segctl_physical_address(env, physical, prot, real_address,
|
||||
access_type, mmu_idx,
|
||||
env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
|
||||
} else {
|
||||
/*
|
||||
* kseg3
|
||||
* XXX: debug segment is not emulated
|
||||
*/
|
||||
ret = get_segctl_physical_address(env, physical, prot, real_address,
|
||||
access_type, mmu_idx,
|
||||
env->CP0_SegCtl0, 0x1FFFFFFF);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void cpu_mips_tlb_flush(CPUMIPSState *env)
|
||||
{
|
||||
/* Flush qemu's TLB and discard all shadowed entries. */
|
||||
@ -403,8 +493,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
|
||||
env->tlb->tlb_in_use = env->tlb->nb_tlb;
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
|
||||
MMUAccessType access_type, int tlb_error)
|
||||
{
|
||||
@ -484,22 +572,6 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
|
||||
env->error_code = error_code;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
hwaddr phys_addr;
|
||||
int prot;
|
||||
|
||||
if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
|
||||
cpu_mmu_index(env, false)) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return phys_addr;
|
||||
}
|
||||
|
||||
#if !defined(TARGET_MIPS64)
|
||||
|
||||
/*
|
||||
@ -833,7 +905,6 @@ refill:
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
||||
MMUAccessType access_type, int mmu_idx,
|
||||
@ -841,14 +912,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
hwaddr physical;
|
||||
int prot;
|
||||
#endif
|
||||
int ret = TLBRET_BADADDR;
|
||||
|
||||
/* data access */
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
/* XXX: put correct access by using cpu_restore_state() correctly */
|
||||
ret = get_physical_address(env, &physical, &prot, address,
|
||||
access_type, mmu_idx);
|
||||
@ -896,29 +964,28 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
||||
if (probe) {
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
raise_mmu_exception(env, address, access_type, ret);
|
||||
do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
|
||||
MMUAccessType access_type)
|
||||
MMUAccessType access_type, uintptr_t retaddr)
|
||||
{
|
||||
hwaddr physical;
|
||||
int prot;
|
||||
int ret = 0;
|
||||
CPUState *cs = env_cpu(env);
|
||||
|
||||
/* data access */
|
||||
ret = get_physical_address(env, &physical, &prot, address, access_type,
|
||||
cpu_mmu_index(env, false));
|
||||
if (ret != TLBRET_MATCH) {
|
||||
raise_mmu_exception(env, address, access_type, ret);
|
||||
return -1LL;
|
||||
} else {
|
||||
if (ret == TLBRET_MATCH) {
|
||||
return physical;
|
||||
}
|
||||
|
||||
raise_mmu_exception(env, address, access_type, ret);
|
||||
cpu_loop_exit_restore(cs, retaddr);
|
||||
}
|
||||
|
||||
static void set_hflags_for_handler(CPUMIPSState *env)
|
||||
@ -964,11 +1031,8 @@ static inline void set_badinstr_registers(CPUMIPSState *env)
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
void mips_cpu_do_interrupt(CPUState *cs)
|
||||
{
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
bool update_badinstr = 0;
|
||||
@ -1271,11 +1335,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
|
||||
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
|
||||
env->CP0_DEPC);
|
||||
}
|
||||
#endif
|
||||
cs->exception_index = EXCP_NONE;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
@ -1340,4 +1402,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* !CONFIG_USER_ONLY */
|
185
target/mips/tcg/sysemu_helper.h.inc
Normal file
185
target/mips/tcg/sysemu_helper.h.inc
Normal file
@ -0,0 +1,185 @@
|
||||
/*
|
||||
* QEMU MIPS sysemu helpers
|
||||
*
|
||||
* Copyright (c) 2004-2005 Jocelyn Mayer
|
||||
* Copyright (c) 2006 Marius Groeger (FPU operations)
|
||||
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
|
||||
* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
|
||||
*
|
||||
* SPDX-License-Identifier: LGPL-2.1-or-later
|
||||
*/
|
||||
|
||||
DEF_HELPER_1(do_semihosting, void, env)
|
||||
|
||||
/* CP0 helpers */
|
||||
DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
|
||||
DEF_HELPER_1(mfc0_mvpconf0, tl, env)
|
||||
DEF_HELPER_1(mfc0_mvpconf1, tl, env)
|
||||
DEF_HELPER_1(mftc0_vpecontrol, tl, env)
|
||||
DEF_HELPER_1(mftc0_vpeconf0, tl, env)
|
||||
DEF_HELPER_1(mfc0_random, tl, env)
|
||||
DEF_HELPER_1(mfc0_tcstatus, tl, env)
|
||||
DEF_HELPER_1(mftc0_tcstatus, tl, env)
|
||||
DEF_HELPER_1(mfc0_tcbind, tl, env)
|
||||
DEF_HELPER_1(mftc0_tcbind, tl, env)
|
||||
DEF_HELPER_1(mfc0_tcrestart, tl, env)
|
||||
DEF_HELPER_1(mftc0_tcrestart, tl, env)
|
||||
DEF_HELPER_1(mfc0_tchalt, tl, env)
|
||||
DEF_HELPER_1(mftc0_tchalt, tl, env)
|
||||
DEF_HELPER_1(mfc0_tccontext, tl, env)
|
||||
DEF_HELPER_1(mftc0_tccontext, tl, env)
|
||||
DEF_HELPER_1(mfc0_tcschedule, tl, env)
|
||||
DEF_HELPER_1(mftc0_tcschedule, tl, env)
|
||||
DEF_HELPER_1(mfc0_tcschefback, tl, env)
|
||||
DEF_HELPER_1(mftc0_tcschefback, tl, env)
|
||||
DEF_HELPER_1(mfc0_count, tl, env)
|
||||
DEF_HELPER_1(mfc0_saar, tl, env)
|
||||
DEF_HELPER_1(mfhc0_saar, tl, env)
|
||||
DEF_HELPER_1(mftc0_entryhi, tl, env)
|
||||
DEF_HELPER_1(mftc0_status, tl, env)
|
||||
DEF_HELPER_1(mftc0_cause, tl, env)
|
||||
DEF_HELPER_1(mftc0_epc, tl, env)
|
||||
DEF_HELPER_1(mftc0_ebase, tl, env)
|
||||
DEF_HELPER_2(mftc0_configx, tl, env, tl)
|
||||
DEF_HELPER_1(mfc0_lladdr, tl, env)
|
||||
DEF_HELPER_1(mfc0_maar, tl, env)
|
||||
DEF_HELPER_1(mfhc0_maar, tl, env)
|
||||
DEF_HELPER_2(mfc0_watchlo, tl, env, i32)
|
||||
DEF_HELPER_2(mfc0_watchhi, tl, env, i32)
|
||||
DEF_HELPER_2(mfhc0_watchhi, tl, env, i32)
|
||||
DEF_HELPER_1(mfc0_debug, tl, env)
|
||||
DEF_HELPER_1(mftc0_debug, tl, env)
|
||||
#ifdef TARGET_MIPS64
|
||||
DEF_HELPER_1(dmfc0_tcrestart, tl, env)
|
||||
DEF_HELPER_1(dmfc0_tchalt, tl, env)
|
||||
DEF_HELPER_1(dmfc0_tccontext, tl, env)
|
||||
DEF_HELPER_1(dmfc0_tcschedule, tl, env)
|
||||
DEF_HELPER_1(dmfc0_tcschefback, tl, env)
|
||||
DEF_HELPER_1(dmfc0_lladdr, tl, env)
|
||||
DEF_HELPER_1(dmfc0_maar, tl, env)
|
||||
DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
|
||||
DEF_HELPER_2(dmfc0_watchhi, tl, env, i32)
|
||||
DEF_HELPER_1(dmfc0_saar, tl, env)
|
||||
#endif /* TARGET_MIPS64 */
|
||||
|
||||
DEF_HELPER_2(mtc0_index, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_vpecontrol, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_vpecontrol, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_vpeconf0, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_vpeconf0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_vpeconf1, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_yqmask, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_vpeopt, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_entrylo0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tcstatus, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tcstatus, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tcbind, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tcbind, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tcrestart, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tcrestart, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tchalt, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tchalt, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tccontext, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tccontext, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tcschedule, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tcschedule, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_tcschefback, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_tcschefback, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_entrylo1, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_context, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_memorymapid, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_pagemask, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_pagegrain, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_segctl0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_segctl1, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_segctl2, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_pwfield, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_pwsize, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_wired, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsconf0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsconf1, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsconf2, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsconf3, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_hwrena, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_pwctl, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_count, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_saari, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_saar, void, env, tl)
|
||||
DEF_HELPER_2(mthc0_saar, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_entryhi, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_entryhi, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_compare, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_status, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_status, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_intctl, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_srsctl, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_cause, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_cause, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_ebase, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_ebase, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_config0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_config2, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_config3, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_config4, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_config5, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_lladdr, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_maar, void, env, tl)
|
||||
DEF_HELPER_2(mthc0_maar, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_maari, void, env, tl)
|
||||
DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
|
||||
DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
|
||||
DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32)
|
||||
DEF_HELPER_2(mtc0_xcontext, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_framemask, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_debug, void, env, tl)
|
||||
DEF_HELPER_2(mttc0_debug, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_performance0, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_errctl, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_taglo, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_datalo, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_taghi, void, env, tl)
|
||||
DEF_HELPER_2(mtc0_datahi, void, env, tl)
|
||||
|
||||
#if defined(TARGET_MIPS64)
|
||||
DEF_HELPER_2(dmtc0_entrylo0, void, env, i64)
|
||||
DEF_HELPER_2(dmtc0_entrylo1, void, env, i64)
|
||||
#endif
|
||||
|
||||
/* MIPS MT functions */
|
||||
DEF_HELPER_2(mftgpr, tl, env, i32)
|
||||
DEF_HELPER_2(mftlo, tl, env, i32)
|
||||
DEF_HELPER_2(mfthi, tl, env, i32)
|
||||
DEF_HELPER_2(mftacx, tl, env, i32)
|
||||
DEF_HELPER_1(mftdsp, tl, env)
|
||||
DEF_HELPER_3(mttgpr, void, env, tl, i32)
|
||||
DEF_HELPER_3(mttlo, void, env, tl, i32)
|
||||
DEF_HELPER_3(mtthi, void, env, tl, i32)
|
||||
DEF_HELPER_3(mttacx, void, env, tl, i32)
|
||||
DEF_HELPER_2(mttdsp, void, env, tl)
|
||||
DEF_HELPER_0(dmt, tl)
|
||||
DEF_HELPER_0(emt, tl)
|
||||
DEF_HELPER_1(dvpe, tl, env)
|
||||
DEF_HELPER_1(evpe, tl, env)
|
||||
|
||||
/* R6 Multi-threading */
|
||||
DEF_HELPER_1(dvp, tl, env)
|
||||
DEF_HELPER_1(evp, tl, env)
|
||||
|
||||
/* TLB */
|
||||
DEF_HELPER_1(tlbwi, void, env)
|
||||
DEF_HELPER_1(tlbwr, void, env)
|
||||
DEF_HELPER_1(tlbp, void, env)
|
||||
DEF_HELPER_1(tlbr, void, env)
|
||||
DEF_HELPER_1(tlbinv, void, env)
|
||||
DEF_HELPER_1(tlbinvf, void, env)
|
||||
DEF_HELPER_3(ginvt, void, env, tl, i32)
|
||||
|
||||
/* Special */
|
||||
DEF_HELPER_1(di, tl, env)
|
||||
DEF_HELPER_1(ei, tl, env)
|
||||
DEF_HELPER_1(eret, void, env)
|
||||
DEF_HELPER_1(eretnc, void, env)
|
||||
DEF_HELPER_1(deret, void, env)
|
||||
DEF_HELPER_3(cache, void, env, tl, i32)
|
64
target/mips/tcg/tcg-internal.h
Normal file
64
target/mips/tcg/tcg-internal.h
Normal file
@ -0,0 +1,64 @@
|
||||
/*
|
||||
* MIPS internal definitions and helpers (TCG accelerator)
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
#ifndef MIPS_TCG_INTERNAL_H
|
||||
#define MIPS_TCG_INTERNAL_H
|
||||
|
||||
#include "tcg/tcg.h"
|
||||
#include "exec/memattrs.h"
|
||||
#include "hw/core/cpu.h"
|
||||
#include "cpu.h"
|
||||
|
||||
void mips_tcg_init(void);
|
||||
|
||||
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
|
||||
void mips_cpu_do_interrupt(CPUState *cpu);
|
||||
bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
|
||||
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
||||
MMUAccessType access_type, int mmu_idx,
|
||||
bool probe, uintptr_t retaddr);
|
||||
void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
|
||||
MMUAccessType access_type,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
|
||||
const char *mips_exception_name(int32_t exception);
|
||||
|
||||
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
|
||||
int error_code, uintptr_t pc);
|
||||
|
||||
static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
|
||||
uint32_t exception,
|
||||
uintptr_t pc)
|
||||
{
|
||||
do_raise_exception_err(env, exception, 0, pc);
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
void mmu_init(CPUMIPSState *env, const mips_def_t *def);
|
||||
|
||||
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
|
||||
|
||||
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
|
||||
uint32_t cpu_mips_get_random(CPUMIPSState *env);
|
||||
|
||||
bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb);
|
||||
|
||||
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
|
||||
MMUAccessType access_type, uintptr_t retaddr);
|
||||
void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
|
||||
vaddr addr, unsigned size,
|
||||
MMUAccessType access_type,
|
||||
int mmu_idx, MemTxAttrs attrs,
|
||||
MemTxResult response, uintptr_t retaddr);
|
||||
void cpu_mips_tlb_flush(CPUMIPSState *env);
|
||||
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
#endif
|
@ -39,6 +39,19 @@
|
||||
#include "fpu_helper.h"
|
||||
#include "translate.h"
|
||||
|
||||
/*
|
||||
* Many sysemu-only helpers are not reachable for user-only.
|
||||
* Define stub generators here, so that we need not either sprinkle
|
||||
* ifdefs through the translator, nor provide the helper function.
|
||||
*/
|
||||
#define STUB_HELPER(NAME, ...) \
|
||||
static inline void gen_helper_##NAME(__VA_ARGS__) \
|
||||
{ g_assert_not_reached(); }
|
||||
|
||||
#ifdef CONFIG_USER_ONLY
|
||||
STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg)
|
||||
#endif
|
||||
|
||||
enum {
|
||||
/* indirect opcode tables */
|
||||
OPC_SPECIAL = (0x00 << 26),
|
||||
@ -1267,13 +1280,6 @@ TCGv_i64 fpu_f64[32];
|
||||
#define DISAS_STOP DISAS_TARGET_0
|
||||
#define DISAS_EXIT DISAS_TARGET_1
|
||||
|
||||
static const char * const regnames[] = {
|
||||
"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
|
||||
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
|
||||
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
|
||||
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
|
||||
};
|
||||
|
||||
static const char * const regnames_HI[] = {
|
||||
"HI0", "HI1", "HI2", "HI3",
|
||||
};
|
||||
@ -1282,13 +1288,6 @@ static const char * const regnames_LO[] = {
|
||||
"LO0", "LO1", "LO2", "LO3",
|
||||
};
|
||||
|
||||
static const char * const fregnames[] = {
|
||||
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
|
||||
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
|
||||
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
|
||||
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
|
||||
};
|
||||
|
||||
/* General purpose registers moves. */
|
||||
void gen_load_gpr(TCGv t, int reg)
|
||||
{
|
||||
@ -1572,11 +1571,13 @@ void gen_move_high32(TCGv ret, TCGv_i64 arg)
|
||||
#endif
|
||||
}
|
||||
|
||||
void check_cp0_enabled(DisasContext *ctx)
|
||||
bool check_cp0_enabled(DisasContext *ctx)
|
||||
{
|
||||
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
|
||||
generate_exception_end(ctx, EXCP_CpU);
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
void check_cp1_enabled(DisasContext *ctx)
|
||||
@ -5945,6 +5946,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
trace_mips_translate_c0("mthc0", register_name, reg, sel);
|
||||
return;
|
||||
|
||||
cp0_unimplemented:
|
||||
qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n",
|
||||
@ -18969,9 +18971,11 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
|
||||
}
|
||||
break;
|
||||
case NM_RDPGPR:
|
||||
check_cp0_enabled(ctx);
|
||||
gen_load_srsgpr(rs, rt);
|
||||
break;
|
||||
case NM_WRPGPR:
|
||||
check_cp0_enabled(ctx);
|
||||
gen_store_srsgpr(rs, rt);
|
||||
break;
|
||||
case NM_WAIT:
|
||||
@ -20957,6 +20961,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
|
||||
gen_ld(ctx, OPC_LHUE, rt, rs, s);
|
||||
break;
|
||||
case NM_CACHEE:
|
||||
check_eva(ctx);
|
||||
check_cp0_enabled(ctx);
|
||||
check_nms_dl_il_sl_tl_l2c(ctx);
|
||||
gen_cache_operation(ctx, rt, rs, s);
|
||||
break;
|
||||
@ -24530,11 +24536,11 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
|
||||
gen_st_cond(ctx, rt, rs, imm, MO_TESL, true);
|
||||
return;
|
||||
case OPC_CACHEE:
|
||||
check_eva(ctx);
|
||||
check_cp0_enabled(ctx);
|
||||
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
|
||||
gen_cache_operation(ctx, rt, rs, imm);
|
||||
}
|
||||
/* Treat as NOP. */
|
||||
return;
|
||||
case OPC_PREFE:
|
||||
check_cp0_enabled(ctx);
|
||||
@ -25593,83 +25599,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
|
||||
translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
|
||||
}
|
||||
|
||||
static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags)
|
||||
{
|
||||
int i;
|
||||
int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
|
||||
|
||||
#define printfpr(fp) \
|
||||
do { \
|
||||
if (is_fpu64) \
|
||||
qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
|
||||
" fd:%13g fs:%13g psu: %13g\n", \
|
||||
(fp)->w[FP_ENDIAN_IDX], (fp)->d, \
|
||||
(double)(fp)->fd, \
|
||||
(double)(fp)->fs[FP_ENDIAN_IDX], \
|
||||
(double)(fp)->fs[!FP_ENDIAN_IDX]); \
|
||||
else { \
|
||||
fpr_t tmp; \
|
||||
tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
|
||||
tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
|
||||
qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
|
||||
" fd:%13g fs:%13g psu:%13g\n", \
|
||||
tmp.w[FP_ENDIAN_IDX], tmp.d, \
|
||||
(double)tmp.fd, \
|
||||
(double)tmp.fs[FP_ENDIAN_IDX], \
|
||||
(double)tmp.fs[!FP_ENDIAN_IDX]); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
||||
qemu_fprintf(f,
|
||||
"CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
|
||||
env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
|
||||
get_float_exception_flags(&env->active_fpu.fp_status));
|
||||
for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
|
||||
qemu_fprintf(f, "%3s: ", fregnames[i]);
|
||||
printfpr(&env->active_fpu.fpr[i]);
|
||||
}
|
||||
|
||||
#undef printfpr
|
||||
}
|
||||
|
||||
void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
int i;
|
||||
|
||||
qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
|
||||
" LO=0x" TARGET_FMT_lx " ds %04x "
|
||||
TARGET_FMT_lx " " TARGET_FMT_ld "\n",
|
||||
env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
|
||||
env->hflags, env->btarget, env->bcond);
|
||||
for (i = 0; i < 32; i++) {
|
||||
if ((i & 3) == 0) {
|
||||
qemu_fprintf(f, "GPR%02d:", i);
|
||||
}
|
||||
qemu_fprintf(f, " %s " TARGET_FMT_lx,
|
||||
regnames[i], env->active_tc.gpr[i]);
|
||||
if ((i & 3) == 3) {
|
||||
qemu_fprintf(f, "\n");
|
||||
}
|
||||
}
|
||||
|
||||
qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
|
||||
TARGET_FMT_lx "\n",
|
||||
env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
|
||||
qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
|
||||
PRIx64 "\n",
|
||||
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
|
||||
qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
|
||||
env->CP0_Config2, env->CP0_Config3);
|
||||
qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
|
||||
env->CP0_Config4, env->CP0_Config5);
|
||||
if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
|
||||
fpu_dump_state(env, f, flags);
|
||||
}
|
||||
}
|
||||
|
||||
void mips_tcg_init(void)
|
||||
{
|
||||
int i;
|
3
target/mips/tcg/user/meson.build
Normal file
3
target/mips/tcg/user/meson.build
Normal file
@ -0,0 +1,3 @@
|
||||
mips_user_ss.add(files(
|
||||
'tlb_helper.c',
|
||||
))
|
64
target/mips/tcg/user/tlb_helper.c
Normal file
64
target/mips/tcg/user/tlb_helper.c
Normal file
@ -0,0 +1,64 @@
|
||||
/*
|
||||
* MIPS TLB (Translation lookaside buffer) helpers.
|
||||
*
|
||||
* Copyright (c) 2004-2005 Jocelyn Mayer
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#include "qemu/osdep.h"
|
||||
|
||||
#include "cpu.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "internal.h"
|
||||
|
||||
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
|
||||
MMUAccessType access_type)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
|
||||
env->error_code = 0;
|
||||
if (access_type == MMU_INST_FETCH) {
|
||||
env->error_code |= EXCP_INST_NOTAVAIL;
|
||||
}
|
||||
|
||||
/* Reference to kernel address from user mode or supervisor mode */
|
||||
/* Reference to supervisor address from user mode */
|
||||
if (access_type == MMU_DATA_STORE) {
|
||||
cs->exception_index = EXCP_AdES;
|
||||
} else {
|
||||
cs->exception_index = EXCP_AdEL;
|
||||
}
|
||||
|
||||
/* Raise exception */
|
||||
if (!(env->hflags & MIPS_HFLAG_DM)) {
|
||||
env->CP0_BadVAddr = address;
|
||||
}
|
||||
}
|
||||
|
||||
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
||||
MMUAccessType access_type, int mmu_idx,
|
||||
bool probe, uintptr_t retaddr)
|
||||
{
|
||||
MIPSCPU *cpu = MIPS_CPU(cs);
|
||||
CPUMIPSState *env = &cpu->env;
|
||||
|
||||
/* data access */
|
||||
raise_mmu_exception(env, address, access_type);
|
||||
do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
|
||||
}
|
||||
|
||||
void mips_cpu_do_interrupt(CPUState *cs)
|
||||
{
|
||||
cs->exception_index = EXCP_NONE;
|
||||
}
|
@ -120,7 +120,12 @@ void gen_reserved_instruction(DisasContext *ctx);
|
||||
|
||||
void check_insn(DisasContext *ctx, uint64_t flags);
|
||||
void check_mips_64(DisasContext *ctx);
|
||||
void check_cp0_enabled(DisasContext *ctx);
|
||||
/**
|
||||
* check_cp0_enabled:
|
||||
* Return %true if CP0 is enabled, otherwise return %false
|
||||
* and emit a 'coprocessor unusable' exception.
|
||||
*/
|
||||
bool check_cp0_enabled(DisasContext *ctx);
|
||||
void check_cp1_enabled(DisasContext *ctx);
|
||||
void check_cp1_64bitmode(DisasContext *ctx);
|
||||
void check_cp1_registers(DisasContext *ctx, int regs);
|
||||
|
Loading…
Reference in New Issue
Block a user