riscv: hart: Add a "hartid-base" property to RISC-V hart array
At present each hart's hartid in a RISC-V hart array is assigned the same value of its index in the hart array. But for a system that has multiple hart arrays, this is not the case any more. Add a new "hartid-base" property so that hartid number can be assigned based on the property value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -29,6 +29,7 @@
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static Property riscv_harts_props[] = {
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static Property riscv_harts_props[] = {
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DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
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DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
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DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
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DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
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DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -47,7 +48,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
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object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
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object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
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sizeof(RISCVCPU), cpu_type,
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sizeof(RISCVCPU), cpu_type,
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&error_abort, NULL);
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&error_abort, NULL);
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s->harts[idx].env.mhartid = idx;
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s->harts[idx].env.mhartid = s->hartid_base + idx;
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qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
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qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
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object_property_set_bool(OBJECT(&s->harts[idx]), true,
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object_property_set_bool(OBJECT(&s->harts[idx]), true,
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"realized", &err);
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"realized", &err);
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@ -35,6 +35,7 @@ typedef struct RISCVHartArrayState {
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/*< public >*/
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/*< public >*/
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uint32_t num_harts;
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uint32_t num_harts;
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uint32_t hartid_base;
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char *cpu_type;
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char *cpu_type;
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RISCVCPU *harts;
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RISCVCPU *harts;
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} RISCVHartArrayState;
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} RISCVHartArrayState;
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