MIPS patches 2017-03-20
Changes: * Fix clang warnings * Fix delay slot detection in gen_msa_branch() * Fix rc4030 interval timer * Fix rc4030 to tranlate memory accesses only when they occur * Fix 4c4030 a mixed declarations and code warning * Update MAINTAINERS file -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.5 (GNU/Linux) iQIVAwUAWM/PCSI464bV95fCAQKEpRAAk01ohpkYPoezmU2r9xzDeh3p6TwecSxy QjSAYsomfREZ/eK4NjHSTrZIFQXJJDUNupw5yLLiwjjqX4lz/VhqF1ELeUSJVw6i o2+h7eSft5uewSYTZPoffvxGywT9FbTOGOgoIcp+i0HKWoZIdovR2Cqt3GcfPAmP IyjMdOHWcBkLpC0MnbD1B6Ty5x9caRlUf+LceuC6/EP6P+Lun4qroLfc+65v64df +hxcYh/05IXtCE4HZIiHfD91BZkmjx4OiWN0+lPWks2kW55x+fQm6ZK8neb9SVv0 6apDMMvygrYQ18ukakK+wZqJag2bvu4hXE6DPka6/0aeQwN7+Z4h7E3EsOD3TJzU K/PGI8BnJwghp4YZXt4F+e60+LyVM3zCXXjFtLQ1FWABIKffg0vyv+rmZRgF0h0C PShsmcNH8icBOfM0uvGNWTReLp7WSkN62gmM1JoKHmYJDt+NuanHTwKowoFvNxws TQGvSH0JrfYTLE6jbXlXoMgEy7ww9Fsx7M7eQwQbZhK9BLAEcL84xmL996/ZmXtb N1TZ/HQTI415vpfj6YtSa6L1MtwswmaNvprQYMdMFZDCfRy6CbumG9USFSiDSYMg 2Gzfa0tDNqy1MSX1jPeybUqcP5Sqe4JOyxLAF7TBHgIy6vhVw4cPfvZK9QWK7Mph AsQ+Pb8sPe4= =jHgS -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170320' into staging MIPS patches 2017-03-20 Changes: * Fix clang warnings * Fix delay slot detection in gen_msa_branch() * Fix rc4030 interval timer * Fix rc4030 to tranlate memory accesses only when they occur * Fix 4c4030 a mixed declarations and code warning * Update MAINTAINERS file # gpg: Signature made Mon 20 Mar 2017 12:46:01 GMT # gpg: using RSA key 0x2238EB86D5F797C2 # gpg: Good signature from "Yongbok Kim <yongbok.kim@imgtec.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA 2B5C 2238 EB86 D5F7 97C2 * remotes/yongbok/tags/mips-20170320: MAINTAINERS: update for MIPS devices dma/rc4030: fix a mixed declarations and code warning dma/rc4030: translate memory accesses only when they occur dma: rc4030: limit interval timer reload value target/mips: fix delay slot detection in gen_msa_branch() target-mips: replace few LOG_DISAS() with trace points target-mips: replace break by goto cp0_unimplemented target-mips: log bad coprocessor0 register accesses with LOG_UNIMP target-mips: remove old & unuseful comments target-mips: fix compiler warnings (clang 5) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
e8b974f1ed
17
MAINTAINERS
17
MAINTAINERS
@ -600,15 +600,28 @@ S: Maintained
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F: hw/mips/mips_malta.c
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Mipssim
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L: qemu-devel@nongnu.org
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S: Orphan
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M: Yongbok Kim <yongbok.kim@imgtec.com>
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S: Odd Fixes
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F: hw/mips/mips_mipssim.c
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F: hw/net/mipsnet.c
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R4000
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M: Aurelien Jarno <aurelien@aurel32.net>
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S: Maintained
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F: hw/mips/mips_r4k.c
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Fulong 2E
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M: Yongbok Kim <yongbok.kim@imgtec.com>
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S: Odd Fixes
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F: hw/mips/mips_fulong2e.c
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Boston
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M: Paul Burton <paul.burton@imgtec.com>
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S: Maintained
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F: hw/core/loader-fit.c
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F: hw/mips/boston.c
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F: hw/pci-host/xilinx-pcie.c
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OpenRISC Machines
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-----------------
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or1k-sim
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@ -157,6 +157,7 @@ trace-events-subdirs += audio
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trace-events-subdirs += net
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trace-events-subdirs += target/arm
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trace-events-subdirs += target/i386
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trace-events-subdirs += target/mips
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trace-events-subdirs += target/sparc
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trace-events-subdirs += target/s390x
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trace-events-subdirs += target/ppc
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162
hw/dma/rc4030.c
162
hw/dma/rc4030.c
@ -34,8 +34,6 @@
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/********************************************************/
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/* rc4030 emulation */
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#define MAX_TL_ENTRIES 512
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typedef struct dma_pagetable_entry {
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int32_t frame;
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int32_t owner;
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@ -91,14 +89,8 @@ typedef struct rc4030State
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qemu_irq timer_irq;
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qemu_irq jazz_bus_irq;
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/* biggest translation table */
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MemoryRegion dma_tt;
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/* translation table memory region alias, added to system RAM */
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MemoryRegion dma_tt_alias;
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/* whole DMA memory region, root of DMA address space */
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MemoryRegion dma_mr;
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/* translation table entry aliases, added to DMA memory region */
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MemoryRegion dma_mrs[MAX_TL_ENTRIES];
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AddressSpace dma_as;
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MemoryRegion iomem_chipset;
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@ -107,8 +99,8 @@ typedef struct rc4030State
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static void set_next_tick(rc4030State *s)
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{
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qemu_irq_lower(s->timer_irq);
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uint32_t tm_hz;
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qemu_irq_lower(s->timer_irq);
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tm_hz = 1000 / (s->itr + 1);
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@ -256,96 +248,6 @@ static uint64_t rc4030_read(void *opaque, hwaddr addr, unsigned int size)
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return val;
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}
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static void rc4030_dma_as_update_one(rc4030State *s, int index, uint32_t frame)
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{
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if (index < MAX_TL_ENTRIES) {
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memory_region_set_enabled(&s->dma_mrs[index], false);
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}
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if (!frame) {
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return;
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}
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if (index >= MAX_TL_ENTRIES) {
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qemu_log_mask(LOG_UNIMP,
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"rc4030: trying to use too high "
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"translation table entry %d (max allowed=%d)",
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index, MAX_TL_ENTRIES);
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return;
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}
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memory_region_set_alias_offset(&s->dma_mrs[index], frame);
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memory_region_set_enabled(&s->dma_mrs[index], true);
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}
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static void rc4030_dma_tt_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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rc4030State *s = opaque;
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/* write memory */
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memcpy(memory_region_get_ram_ptr(&s->dma_tt) + addr, &data, size);
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/* update dma address space (only if frame field has been written) */
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if (addr % sizeof(dma_pagetable_entry) == 0) {
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int index = addr / sizeof(dma_pagetable_entry);
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memory_region_transaction_begin();
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rc4030_dma_as_update_one(s, index, (uint32_t)data);
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memory_region_transaction_commit();
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}
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}
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static const MemoryRegionOps rc4030_dma_tt_ops = {
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.write = rc4030_dma_tt_write,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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};
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static void rc4030_dma_tt_update(rc4030State *s, uint32_t new_tl_base,
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uint32_t new_tl_limit)
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{
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int entries, i;
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dma_pagetable_entry *dma_tl_contents;
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if (s->dma_tl_limit) {
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/* write old dma tl table to physical memory */
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memory_region_del_subregion(get_system_memory(), &s->dma_tt_alias);
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cpu_physical_memory_write(s->dma_tl_limit & 0x7fffffff,
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memory_region_get_ram_ptr(&s->dma_tt),
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memory_region_size(&s->dma_tt_alias));
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}
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object_unparent(OBJECT(&s->dma_tt_alias));
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s->dma_tl_base = new_tl_base;
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s->dma_tl_limit = new_tl_limit;
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new_tl_base &= 0x7fffffff;
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if (s->dma_tl_limit) {
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uint64_t dma_tt_size;
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if (s->dma_tl_limit <= memory_region_size(&s->dma_tt)) {
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dma_tt_size = s->dma_tl_limit;
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} else {
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dma_tt_size = memory_region_size(&s->dma_tt);
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}
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memory_region_init_alias(&s->dma_tt_alias, OBJECT(s),
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"dma-table-alias",
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&s->dma_tt, 0, dma_tt_size);
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dma_tl_contents = memory_region_get_ram_ptr(&s->dma_tt);
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cpu_physical_memory_read(new_tl_base, dma_tl_contents, dma_tt_size);
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memory_region_transaction_begin();
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entries = dma_tt_size / sizeof(dma_pagetable_entry);
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for (i = 0; i < entries; i++) {
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rc4030_dma_as_update_one(s, i, dma_tl_contents[i].frame);
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}
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memory_region_add_subregion(get_system_memory(), new_tl_base,
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&s->dma_tt_alias);
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memory_region_transaction_commit();
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} else {
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memory_region_init(&s->dma_tt_alias, OBJECT(s),
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"dma-table-alias", 0);
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}
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}
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static void rc4030_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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@ -362,11 +264,11 @@ static void rc4030_write(void *opaque, hwaddr addr, uint64_t data,
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break;
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/* DMA transl. table base */
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case 0x0018:
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rc4030_dma_tt_update(s, val, s->dma_tl_limit);
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s->dma_tl_base = val;
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break;
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/* DMA transl. table limit */
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case 0x0020:
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rc4030_dma_tt_update(s, s->dma_tl_base, val);
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s->dma_tl_limit = val;
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break;
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/* DMA transl. table invalidated */
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case 0x0028:
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@ -460,7 +362,7 @@ static void rc4030_write(void *opaque, hwaddr addr, uint64_t data,
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break;
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/* Interval timer reload */
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case 0x0228:
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s->itr = val;
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s->itr = val & 0x01FF;
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qemu_irq_lower(s->timer_irq);
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set_next_tick(s);
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break;
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@ -586,6 +488,38 @@ static const MemoryRegionOps jazzio_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static IOMMUTLBEntry rc4030_dma_translate(MemoryRegion *iommu, hwaddr addr,
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bool is_write)
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{
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rc4030State *s = container_of(iommu, rc4030State, dma_mr);
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IOMMUTLBEntry ret = {
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.target_as = &address_space_memory,
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.iova = addr & ~(DMA_PAGESIZE - 1),
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.translated_addr = 0,
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.addr_mask = DMA_PAGESIZE - 1,
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.perm = IOMMU_NONE,
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};
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uint64_t i, entry_address;
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dma_pagetable_entry entry;
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i = addr / DMA_PAGESIZE;
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if (i < s->dma_tl_limit / sizeof(entry)) {
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entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry);
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if (address_space_read(ret.target_as, entry_address,
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MEMTXATTRS_UNSPECIFIED, (unsigned char *)&entry,
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sizeof(entry)) == MEMTX_OK) {
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ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1);
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ret.perm = IOMMU_RW;
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}
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}
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return ret;
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}
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static const MemoryRegionIOMMUOps rc4030_dma_ops = {
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.translate = rc4030_dma_translate,
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};
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static void rc4030_reset(DeviceState *dev)
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{
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rc4030State *s = RC4030(dev);
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@ -596,7 +530,6 @@ static void rc4030_reset(DeviceState *dev)
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s->invalid_address_register = 0;
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memset(s->dma_regs, 0, sizeof(s->dma_regs));
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rc4030_dma_tt_update(s, 0, 0);
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s->remote_failed_address = s->memory_failed_address = 0;
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s->cache_maint = 0;
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@ -735,7 +668,6 @@ static void rc4030_realize(DeviceState *dev, Error **errp)
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{
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rc4030State *s = RC4030(dev);
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Object *o = OBJECT(dev);
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int i;
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s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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rc4030_periodic_timer, s);
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@ -745,37 +677,19 @@ static void rc4030_realize(DeviceState *dev, Error **errp)
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memory_region_init_io(&s->iomem_jazzio, NULL, &jazzio_ops, s,
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"rc4030.jazzio", 0x00001000);
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memory_region_init_rom_device(&s->dma_tt, o,
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&rc4030_dma_tt_ops, s, "dma-table",
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MAX_TL_ENTRIES * sizeof(dma_pagetable_entry),
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NULL);
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memory_region_init(&s->dma_tt_alias, o, "dma-table-alias", 0);
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memory_region_init(&s->dma_mr, o, "dma", INT32_MAX);
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for (i = 0; i < MAX_TL_ENTRIES; ++i) {
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memory_region_init_alias(&s->dma_mrs[i], o, "dma-alias",
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get_system_memory(), 0, DMA_PAGESIZE);
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memory_region_set_enabled(&s->dma_mrs[i], false);
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memory_region_add_subregion(&s->dma_mr, i * DMA_PAGESIZE,
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&s->dma_mrs[i]);
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}
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memory_region_init_iommu(&s->dma_mr, o, &rc4030_dma_ops,
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"rc4030.dma", UINT32_MAX);
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address_space_init(&s->dma_as, &s->dma_mr, "rc4030-dma");
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}
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static void rc4030_unrealize(DeviceState *dev, Error **errp)
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{
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rc4030State *s = RC4030(dev);
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int i;
|
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|
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timer_free(s->periodic_timer);
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|
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address_space_destroy(&s->dma_as);
|
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object_unparent(OBJECT(&s->dma_tt));
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object_unparent(OBJECT(&s->dma_tt_alias));
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object_unparent(OBJECT(&s->dma_mr));
|
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for (i = 0; i < MAX_TL_ENTRIES; ++i) {
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memory_region_del_subregion(&s->dma_mr, &s->dma_mrs[i]);
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object_unparent(OBJECT(&s->dma_mrs[i]));
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||||
}
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||||
}
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||||
|
||||
static void rc4030_class_init(ObjectClass *klass, void *class_data)
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||||
|
||||
@ -450,10 +450,18 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
|
||||
access_type = ACCESS_INT;
|
||||
ret = get_physical_address(env, &physical, &prot,
|
||||
address, rw, access_type);
|
||||
qemu_log_mask(CPU_LOG_MMU,
|
||||
"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
|
||||
" prot %d\n",
|
||||
__func__, address, ret, physical, prot);
|
||||
switch (ret) {
|
||||
case TLBRET_MATCH:
|
||||
qemu_log_mask(CPU_LOG_MMU,
|
||||
"%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
|
||||
" prot %d\n", __func__, address, physical, prot);
|
||||
break;
|
||||
default:
|
||||
qemu_log_mask(CPU_LOG_MMU,
|
||||
"%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
|
||||
ret);
|
||||
break;
|
||||
}
|
||||
if (ret == TLBRET_MATCH) {
|
||||
tlb_set_page(cs, address & TARGET_PAGE_MASK,
|
||||
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
|
||||
|
||||
5
target/mips/trace-events
Normal file
5
target/mips/trace-events
Normal file
@ -0,0 +1,5 @@
|
||||
# See docs/tracing.txt for syntax documentation.
|
||||
|
||||
# target/mips/translate.c
|
||||
mips_translate_c0(const char *instr, const char *rn, int reg, int sel) "%s %s (reg %d sel %d)"
|
||||
mips_translate_tr(const char *instr, int rt, int u, int sel, int h) "%s (reg %d u %d sel %d h %d)"
|
||||
@ -33,6 +33,7 @@
|
||||
#include "sysemu/kvm.h"
|
||||
#include "exec/semihost.h"
|
||||
|
||||
#include "target/mips/trace.h"
|
||||
#include "trace-tcg.h"
|
||||
#include "exec/log.h"
|
||||
|
||||
@ -4866,13 +4867,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
|
||||
(void)rn; /* avoid a compiler warning */
|
||||
LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
trace_mips_translate_c0("mfhc0", rn, reg, sel);
|
||||
return;
|
||||
|
||||
cp0_unimplemented:
|
||||
LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
tcg_gen_movi_tl(arg, 0);
|
||||
}
|
||||
|
||||
@ -4941,10 +4940,10 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
trace_mips_translate_c0("mthc0", rn, reg, sel);
|
||||
|
||||
(void)rn; /* avoid a compiler warning */
|
||||
cp0_unimplemented:
|
||||
LOG_DISAS("mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
}
|
||||
|
||||
static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
|
||||
@ -5137,7 +5136,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
// gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
|
||||
rn = "ContextConfig";
|
||||
goto cp0_unimplemented;
|
||||
// break;
|
||||
case 2:
|
||||
CP0_CHECK(ctx->ulri);
|
||||
tcg_gen_ld32s_tl(arg, cpu_env,
|
||||
@ -5459,19 +5457,19 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
case 1:
|
||||
// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
|
||||
rn = "TraceControl";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 2:
|
||||
// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
|
||||
rn = "TraceControl2";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 3:
|
||||
// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
|
||||
rn = "UserTraceData";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 4:
|
||||
// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
|
||||
rn = "TraceBPC";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
@ -5497,31 +5495,31 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
case 1:
|
||||
// gen_helper_mfc0_performance1(arg);
|
||||
rn = "Performance1";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 2:
|
||||
// gen_helper_mfc0_performance2(arg);
|
||||
rn = "Performance2";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 3:
|
||||
// gen_helper_mfc0_performance3(arg);
|
||||
rn = "Performance3";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 4:
|
||||
// gen_helper_mfc0_performance4(arg);
|
||||
rn = "Performance4";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 5:
|
||||
// gen_helper_mfc0_performance5(arg);
|
||||
rn = "Performance5";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 6:
|
||||
// gen_helper_mfc0_performance6(arg);
|
||||
rn = "Performance6";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 7:
|
||||
// gen_helper_mfc0_performance7(arg);
|
||||
rn = "Performance7";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
@ -5623,12 +5621,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
(void)rn; /* avoid a compiler warning */
|
||||
LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
trace_mips_translate_c0("mfc0", rn, reg, sel);
|
||||
return;
|
||||
|
||||
cp0_unimplemented:
|
||||
LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
gen_mfc0_unimplemented(ctx, arg);
|
||||
}
|
||||
|
||||
@ -5791,7 +5788,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
|
||||
rn = "ContextConfig";
|
||||
goto cp0_unimplemented;
|
||||
// break;
|
||||
case 2:
|
||||
CP0_CHECK(ctx->ulri);
|
||||
tcg_gen_st_tl(arg, cpu_env,
|
||||
@ -6118,13 +6114,13 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
rn = "TraceControl";
|
||||
/* Stop translation as we may have switched the execution mode */
|
||||
ctx->bstate = BS_STOP;
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 2:
|
||||
// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
|
||||
rn = "TraceControl2";
|
||||
/* Stop translation as we may have switched the execution mode */
|
||||
ctx->bstate = BS_STOP;
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 3:
|
||||
/* Stop translation as we may have switched the execution mode */
|
||||
ctx->bstate = BS_STOP;
|
||||
@ -6132,13 +6128,13 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
rn = "UserTraceData";
|
||||
/* Stop translation as we may have switched the execution mode */
|
||||
ctx->bstate = BS_STOP;
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 4:
|
||||
// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
|
||||
/* Stop translation as we may have switched the execution mode */
|
||||
ctx->bstate = BS_STOP;
|
||||
rn = "TraceBPC";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
@ -6163,31 +6159,31 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
case 1:
|
||||
// gen_helper_mtc0_performance1(arg);
|
||||
rn = "Performance1";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 2:
|
||||
// gen_helper_mtc0_performance2(arg);
|
||||
rn = "Performance2";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 3:
|
||||
// gen_helper_mtc0_performance3(arg);
|
||||
rn = "Performance3";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 4:
|
||||
// gen_helper_mtc0_performance4(arg);
|
||||
rn = "Performance4";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 5:
|
||||
// gen_helper_mtc0_performance5(arg);
|
||||
rn = "Performance5";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 6:
|
||||
// gen_helper_mtc0_performance6(arg);
|
||||
rn = "Performance6";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 7:
|
||||
// gen_helper_mtc0_performance7(arg);
|
||||
rn = "Performance7";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
@ -6286,8 +6282,8 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
(void)rn; /* avoid a compiler warning */
|
||||
LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
trace_mips_translate_c0("mtc0", rn, reg, sel);
|
||||
|
||||
/* For simplicity assume that all writes can cause interrupts. */
|
||||
if (ctx->tb->cflags & CF_USE_ICOUNT) {
|
||||
gen_io_end();
|
||||
@ -6296,7 +6292,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
return;
|
||||
|
||||
cp0_unimplemented:
|
||||
LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
}
|
||||
|
||||
#if defined(TARGET_MIPS64)
|
||||
@ -6454,7 +6450,6 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
// gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
|
||||
rn = "ContextConfig";
|
||||
goto cp0_unimplemented;
|
||||
// break;
|
||||
case 2:
|
||||
CP0_CHECK(ctx->ulri);
|
||||
tcg_gen_ld_tl(arg, cpu_env,
|
||||
@ -6769,19 +6764,19 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
case 1:
|
||||
// gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */
|
||||
rn = "TraceControl";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 2:
|
||||
// gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */
|
||||
rn = "TraceControl2";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 3:
|
||||
// gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */
|
||||
rn = "UserTraceData";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 4:
|
||||
// gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */
|
||||
rn = "TraceBPC";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
@ -6806,31 +6801,31 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
case 1:
|
||||
// gen_helper_dmfc0_performance1(arg);
|
||||
rn = "Performance1";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 2:
|
||||
// gen_helper_dmfc0_performance2(arg);
|
||||
rn = "Performance2";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 3:
|
||||
// gen_helper_dmfc0_performance3(arg);
|
||||
rn = "Performance3";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 4:
|
||||
// gen_helper_dmfc0_performance4(arg);
|
||||
rn = "Performance4";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 5:
|
||||
// gen_helper_dmfc0_performance5(arg);
|
||||
rn = "Performance5";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 6:
|
||||
// gen_helper_dmfc0_performance6(arg);
|
||||
rn = "Performance6";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 7:
|
||||
// gen_helper_dmfc0_performance7(arg);
|
||||
rn = "Performance7";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
@ -6926,12 +6921,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
(void)rn; /* avoid a compiler warning */
|
||||
LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
trace_mips_translate_c0("dmfc0", rn, reg, sel);
|
||||
return;
|
||||
|
||||
cp0_unimplemented:
|
||||
LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
gen_mfc0_unimplemented(ctx, arg);
|
||||
}
|
||||
|
||||
@ -7092,7 +7086,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
|
||||
rn = "ContextConfig";
|
||||
goto cp0_unimplemented;
|
||||
// break;
|
||||
case 2:
|
||||
CP0_CHECK(ctx->ulri);
|
||||
tcg_gen_st_tl(arg, cpu_env,
|
||||
@ -7421,25 +7414,25 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
/* Stop translation as we may have switched the execution mode */
|
||||
ctx->bstate = BS_STOP;
|
||||
rn = "TraceControl";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 2:
|
||||
// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
|
||||
/* Stop translation as we may have switched the execution mode */
|
||||
ctx->bstate = BS_STOP;
|
||||
rn = "TraceControl2";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 3:
|
||||
// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
|
||||
/* Stop translation as we may have switched the execution mode */
|
||||
ctx->bstate = BS_STOP;
|
||||
rn = "UserTraceData";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 4:
|
||||
// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
|
||||
/* Stop translation as we may have switched the execution mode */
|
||||
ctx->bstate = BS_STOP;
|
||||
rn = "TraceBPC";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
@ -7464,31 +7457,31 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
case 1:
|
||||
// gen_helper_mtc0_performance1(cpu_env, arg);
|
||||
rn = "Performance1";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 2:
|
||||
// gen_helper_mtc0_performance2(cpu_env, arg);
|
||||
rn = "Performance2";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 3:
|
||||
// gen_helper_mtc0_performance3(cpu_env, arg);
|
||||
rn = "Performance3";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 4:
|
||||
// gen_helper_mtc0_performance4(cpu_env, arg);
|
||||
rn = "Performance4";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 5:
|
||||
// gen_helper_mtc0_performance5(cpu_env, arg);
|
||||
rn = "Performance5";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 6:
|
||||
// gen_helper_mtc0_performance6(cpu_env, arg);
|
||||
rn = "Performance6";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
case 7:
|
||||
// gen_helper_mtc0_performance7(cpu_env, arg);
|
||||
rn = "Performance7";
|
||||
// break;
|
||||
goto cp0_unimplemented;
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
@ -7587,8 +7580,8 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
(void)rn; /* avoid a compiler warning */
|
||||
LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
trace_mips_translate_c0("dmtc0", rn, reg, sel);
|
||||
|
||||
/* For simplicity assume that all writes can cause interrupts. */
|
||||
if (ctx->tb->cflags & CF_USE_ICOUNT) {
|
||||
gen_io_end();
|
||||
@ -7597,7 +7590,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
||||
return;
|
||||
|
||||
cp0_unimplemented:
|
||||
LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
||||
}
|
||||
#endif /* TARGET_MIPS64 */
|
||||
|
||||
@ -7807,7 +7800,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
|
||||
default:
|
||||
goto die;
|
||||
}
|
||||
LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
|
||||
trace_mips_translate_tr("mftr", rt, u, sel, h);
|
||||
gen_store_gpr(t0, rd);
|
||||
tcg_temp_free(t0);
|
||||
return;
|
||||
@ -8012,7 +8005,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
|
||||
default:
|
||||
goto die;
|
||||
}
|
||||
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
|
||||
trace_mips_translate_tr("mttr", rd, u, sel, h);
|
||||
tcg_temp_free(t0);
|
||||
return;
|
||||
|
||||
@ -18169,7 +18162,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
|
||||
|
||||
check_msa_access(ctx);
|
||||
|
||||
if (ctx->insn_flags & ISA_MIPS32R6 && ctx->hflags & MIPS_HFLAG_BMASK) {
|
||||
if (ctx->hflags & MIPS_HFLAG_BMASK) {
|
||||
generate_exception_end(ctx, EXCP_RI);
|
||||
return;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user