openpic: convert to vmstate
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Mark Cave-Ayland
Alexander Graf
parent
2ada66f944
commit
e5f6e7327a
@ -207,6 +207,7 @@ typedef enum IRQType {
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typedef struct IRQQueue {
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unsigned long *queue;
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int32_t queue_size; /* Only used for VMSTATE_BITMAP */
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int next;
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int priority;
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} IRQQueue;
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@ -242,6 +243,15 @@ typedef struct IRQSource {
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#define IDR_EP 0x80000000 /* external pin */
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#define IDR_CI 0x40000000 /* critical interrupt */
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typedef struct OpenPICTimer {
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uint32_t tccr; /* Global timer current count register */
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uint32_t tbcr; /* Global timer base count register */
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} OpenPICTimer;
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typedef struct OpenPICMSI {
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uint32_t msir; /* Shared Message Signaled Interrupt Register */
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} OpenPICMSI;
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typedef struct IRQDest {
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int32_t ctpr; /* CPU current task priority */
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IRQQueue raised;
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@ -290,14 +300,9 @@ typedef struct OpenPICState {
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IRQDest dst[MAX_CPU];
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uint32_t nb_cpus;
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/* Timer registers */
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struct {
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uint32_t tccr; /* Global timer current count register */
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uint32_t tbcr; /* Global timer base count register */
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} timers[OPENPIC_MAX_TMR];
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OpenPICTimer timers[OPENPIC_MAX_TMR];
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/* Shared MSI registers */
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struct {
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uint32_t msir; /* Shared Message Signaled Interrupt Register */
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} msi[MAX_MSI];
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OpenPICMSI msi[MAX_MSI];
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uint32_t max_irq;
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uint32_t irq_ipi0;
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uint32_t irq_tim0;
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@ -1289,130 +1294,6 @@ static const MemoryRegionOps openpic_summary_ops_be = {
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},
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};
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static void openpic_save_IRQ_queue(QEMUFile* f, IRQQueue *q)
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{
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unsigned int i;
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for (i = 0; i < BITS_TO_LONGS(IRQQUEUE_SIZE_BITS); i++) {
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/* Always put the lower half of a 64-bit long first, in case we
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* restore on a 32-bit host. The least significant bits correspond
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* to lower IRQ numbers in the bitmap.
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*/
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qemu_put_be32(f, (uint32_t)q->queue[i]);
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#if LONG_MAX > 0x7FFFFFFF
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qemu_put_be32(f, (uint32_t)(q->queue[i] >> 32));
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#endif
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}
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qemu_put_sbe32s(f, &q->next);
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qemu_put_sbe32s(f, &q->priority);
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}
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static void openpic_save(QEMUFile* f, void *opaque)
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{
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OpenPICState *opp = (OpenPICState *)opaque;
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unsigned int i;
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qemu_put_be32s(f, &opp->gcr);
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qemu_put_be32s(f, &opp->vir);
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qemu_put_be32s(f, &opp->pir);
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qemu_put_be32s(f, &opp->spve);
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qemu_put_be32s(f, &opp->tfrr);
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qemu_put_be32s(f, &opp->nb_cpus);
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for (i = 0; i < opp->nb_cpus; i++) {
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qemu_put_sbe32s(f, &opp->dst[i].ctpr);
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openpic_save_IRQ_queue(f, &opp->dst[i].raised);
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openpic_save_IRQ_queue(f, &opp->dst[i].servicing);
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qemu_put_buffer(f, (uint8_t *)&opp->dst[i].outputs_active,
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sizeof(opp->dst[i].outputs_active));
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}
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for (i = 0; i < OPENPIC_MAX_TMR; i++) {
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qemu_put_be32s(f, &opp->timers[i].tccr);
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qemu_put_be32s(f, &opp->timers[i].tbcr);
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}
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for (i = 0; i < opp->max_irq; i++) {
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qemu_put_be32s(f, &opp->src[i].ivpr);
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qemu_put_be32s(f, &opp->src[i].idr);
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qemu_put_be32s(f, &opp->src[i].destmask);
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qemu_put_sbe32s(f, &opp->src[i].last_cpu);
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qemu_put_sbe32s(f, &opp->src[i].pending);
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}
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}
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static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
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{
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unsigned int i;
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for (i = 0; i < BITS_TO_LONGS(IRQQUEUE_SIZE_BITS); i++) {
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unsigned long val;
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val = qemu_get_be32(f);
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#if LONG_MAX > 0x7FFFFFFF
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val <<= 32;
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val |= qemu_get_be32(f);
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#endif
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q->queue[i] = val;
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}
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qemu_get_sbe32s(f, &q->next);
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qemu_get_sbe32s(f, &q->priority);
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}
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static int openpic_load(QEMUFile* f, void *opaque, int version_id)
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{
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OpenPICState *opp = (OpenPICState *)opaque;
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unsigned int i, nb_cpus;
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if (version_id != 2) {
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return -EINVAL;
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}
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qemu_get_be32s(f, &opp->gcr);
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qemu_get_be32s(f, &opp->vir);
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qemu_get_be32s(f, &opp->pir);
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qemu_get_be32s(f, &opp->spve);
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qemu_get_be32s(f, &opp->tfrr);
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qemu_get_be32s(f, &nb_cpus);
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if (opp->nb_cpus != nb_cpus) {
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return -EINVAL;
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}
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assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
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for (i = 0; i < opp->nb_cpus; i++) {
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qemu_get_sbe32s(f, &opp->dst[i].ctpr);
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openpic_load_IRQ_queue(f, &opp->dst[i].raised);
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openpic_load_IRQ_queue(f, &opp->dst[i].servicing);
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qemu_get_buffer(f, (uint8_t *)&opp->dst[i].outputs_active,
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sizeof(opp->dst[i].outputs_active));
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}
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for (i = 0; i < OPENPIC_MAX_TMR; i++) {
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qemu_get_be32s(f, &opp->timers[i].tccr);
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qemu_get_be32s(f, &opp->timers[i].tbcr);
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}
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for (i = 0; i < opp->max_irq; i++) {
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uint32_t val;
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val = qemu_get_be32(f);
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write_IRQreg_ivpr(opp, i, val);
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val = qemu_get_be32(f);
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write_IRQreg_idr(opp, i, val);
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qemu_get_be32s(f, &opp->src[i].destmask);
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qemu_get_sbe32s(f, &opp->src[i].last_cpu);
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qemu_get_sbe32s(f, &opp->src[i].pending);
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}
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return 0;
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}
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static void openpic_reset(DeviceState *d)
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{
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OpenPICState *opp = OPENPIC(d);
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@ -1527,6 +1408,110 @@ static void map_list(OpenPICState *opp, const MemReg *list, int *count)
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}
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}
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static const VMStateDescription vmstate_openpic_irq_queue = {
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.name = "openpic_irq_queue",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_BITMAP(queue, IRQQueue, 0, queue_size),
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VMSTATE_INT32(next, IRQQueue),
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VMSTATE_INT32(priority, IRQQueue),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_openpic_irqdest = {
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.name = "openpic_irqdest",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(ctpr, IRQDest),
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VMSTATE_STRUCT(raised, IRQDest, 0, vmstate_openpic_irq_queue,
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IRQQueue),
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VMSTATE_STRUCT(servicing, IRQDest, 0, vmstate_openpic_irq_queue,
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IRQQueue),
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VMSTATE_UINT32_ARRAY(outputs_active, IRQDest, OPENPIC_OUTPUT_NB),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_openpic_irqsource = {
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.name = "openpic_irqsource",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(ivpr, IRQSource),
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VMSTATE_UINT32(idr, IRQSource),
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VMSTATE_UINT32(destmask, IRQSource),
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VMSTATE_INT32(last_cpu, IRQSource),
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VMSTATE_INT32(pending, IRQSource),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_openpic_timer = {
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.name = "openpic_timer",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(tccr, OpenPICTimer),
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VMSTATE_UINT32(tbcr, OpenPICTimer),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_openpic_msi = {
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.name = "openpic_msi",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(msir, OpenPICMSI),
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VMSTATE_END_OF_LIST()
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}
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};
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static int openpic_post_load(void *opaque, int version_id)
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{
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OpenPICState *opp = (OpenPICState *)opaque;
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int i;
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/* Update internal ivpr and idr variables */
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for (i = 0; i < opp->max_irq; i++) {
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write_IRQreg_idr(opp, i, opp->src[i].idr);
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write_IRQreg_ivpr(opp, i, opp->src[i].ivpr);
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}
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return 0;
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}
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static const VMStateDescription vmstate_openpic = {
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.name = "openpic",
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.version_id = 3,
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.minimum_version_id = 3,
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.post_load = openpic_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(gcr, OpenPICState),
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VMSTATE_UINT32(vir, OpenPICState),
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VMSTATE_UINT32(pir, OpenPICState),
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VMSTATE_UINT32(spve, OpenPICState),
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VMSTATE_UINT32(tfrr, OpenPICState),
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VMSTATE_UINT32(max_irq, OpenPICState),
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VMSTATE_STRUCT_VARRAY_UINT32(src, OpenPICState, max_irq, 0,
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vmstate_openpic_irqsource, IRQSource),
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VMSTATE_UINT32_EQUAL(nb_cpus, OpenPICState),
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VMSTATE_STRUCT_VARRAY_UINT32(dst, OpenPICState, nb_cpus, 0,
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vmstate_openpic_irqdest, IRQDest),
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VMSTATE_STRUCT_ARRAY(timers, OpenPICState, OPENPIC_MAX_TMR, 0,
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vmstate_openpic_timer, OpenPICTimer),
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VMSTATE_STRUCT_ARRAY(msi, OpenPICState, MAX_MSI, 0,
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vmstate_openpic_msi, OpenPICMSI),
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VMSTATE_UINT32(irq_ipi0, OpenPICState),
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VMSTATE_UINT32(irq_tim0, OpenPICState),
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VMSTATE_UINT32(irq_msi, OpenPICState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void openpic_init(Object *obj)
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{
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OpenPICState *opp = OPENPIC(obj);
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@ -1634,13 +1619,12 @@ static void openpic_realize(DeviceState *dev, Error **errp)
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sysbus_init_irq(d, &opp->dst[i].irqs[j]);
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}
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opp->dst[i].raised.queue_size = IRQQUEUE_SIZE_BITS;
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opp->dst[i].raised.queue = bitmap_new(IRQQUEUE_SIZE_BITS);
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opp->dst[i].servicing.queue_size = IRQQUEUE_SIZE_BITS;
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opp->dst[i].servicing.queue = bitmap_new(IRQQUEUE_SIZE_BITS);
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}
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register_savevm(dev, "openpic", 0, 2,
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openpic_save, openpic_load, opp);
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sysbus_init_mmio(d, &opp->mem);
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qdev_init_gpio_in(dev, openpic_set_irq, opp->max_irq);
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}
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@ -1658,6 +1642,7 @@ static void openpic_class_init(ObjectClass *oc, void *data)
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dc->realize = openpic_realize;
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dc->props = openpic_properties;
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dc->reset = openpic_reset;
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dc->vmsd = &vmstate_openpic;
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}
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static const TypeInfo openpic_info = {
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