eepro100: Fix endianness issues
Like other Intel devices, e100 (eepro100) uses little endian byte order. This patch was tested with these combinations: i386 host, i386 + mipsel guests (le-le) mipsel host, i386 guest (le-le) i386 host, mips + ppc guests (le-be) mips host, i386 guest (be-le) mips and mipsel hosts were emulated machines. v2: Use prefix for new functions. Add the same prefix to stl_le_phys. Fix alignment of mem (needed for word/dword reads/writes). Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Stefan Weil
Michael S. Tsirkin
parent
792f1d6394
commit
e5e23ab83b
141
hw/eepro100.c
141
hw/eepro100.c
@ -20,11 +20,10 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Tested features (i82559):
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* PXE boot (i386) ok
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* PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
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* Linux networking (i386) ok
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*
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* Untested:
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* non-i386 platforms
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* Windows networking
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*
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* References:
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@ -139,7 +138,7 @@ typedef struct {
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/* Offsets to the various registers.
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All accesses need not be longword aligned. */
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enum speedo_offsets {
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typedef enum {
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SCBStatus = 0, /* Status Word. */
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SCBAck = 1,
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SCBCmd = 2, /* Rx/Command Unit command and status. */
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@ -154,7 +153,7 @@ enum speedo_offsets {
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SCBpmdr = 27, /* Power Management Driver. */
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SCBgctrl = 28, /* General Control. */
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SCBgstat = 29, /* General Status. */
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};
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} E100RegisterOffset;
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/* A speedo3 transmit buffer descriptor with two buffers... */
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typedef struct {
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@ -258,11 +257,13 @@ typedef struct {
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/* Statistical counters. Also used for wake-up packet (i82559). */
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eepro100_stats_t statistics;
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/* Data in mem is always in the byte order of the controller (le).
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* It must be dword aligned to allow direct access to 32 bit values. */
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uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));;
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/* Configuration bytes. */
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uint8_t configuration[22];
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/* Data in mem is always in the byte order of the controller (le). */
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uint8_t mem[PCI_MEM_SIZE];
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/* vmstate for each particular nic */
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VMStateDescription *vmstate;
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@ -316,8 +317,33 @@ static const uint16_t eepro100_mdi_mask[] = {
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0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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};
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/* XXX: optimize */
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static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
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/* Read a 16 bit little endian value from physical memory. */
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static uint16_t e100_ldw_le_phys(target_phys_addr_t addr)
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{
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/* Load 16 bit (little endian) word from emulated hardware. */
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uint16_t val;
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cpu_physical_memory_read(addr, &val, sizeof(val));
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return le16_to_cpu(val);
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}
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/* Read a 32 bit little endian value from physical memory. */
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static uint32_t e100_ldl_le_phys(target_phys_addr_t addr)
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{
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/* Load 32 bit (little endian) word from emulated hardware. */
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uint32_t val;
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cpu_physical_memory_read(addr, &val, sizeof(val));
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return le32_to_cpu(val);
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}
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/* Write a 16 bit little endian value to physical memory. */
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static void e100_stw_le_phys(target_phys_addr_t addr, uint16_t val)
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{
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val = cpu_to_le16(val);
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cpu_physical_memory_write(addr, &val, sizeof(val));
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}
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/* Write a 32 bit little endian value to physical memory. */
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static void e100_stl_le_phys(target_phys_addr_t addr, uint32_t val)
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{
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val = cpu_to_le32(val);
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cpu_physical_memory_write(addr, &val, sizeof(val));
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@ -348,6 +374,36 @@ static unsigned compute_mcast_idx(const uint8_t * ep)
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return (crc & BITS(7, 2)) >> 2;
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}
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/* Read a 16 bit control/status (CSR) register. */
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static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
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{
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assert(!((uintptr_t)&s->mem[addr] & 1));
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return le16_to_cpup((uint16_t *)&s->mem[addr]);
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}
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/* Read a 32 bit control/status (CSR) register. */
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static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
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{
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assert(!((uintptr_t)&s->mem[addr] & 3));
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return le32_to_cpup((uint32_t *)&s->mem[addr]);
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}
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/* Write a 16 bit control/status (CSR) register. */
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static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
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uint16_t val)
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{
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assert(!((uintptr_t)&s->mem[addr] & 1));
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cpu_to_le16w((uint16_t *)&s->mem[addr], val);
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}
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/* Read a 32 bit control/status (CSR) register. */
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static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
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uint32_t val)
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{
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assert(!((uintptr_t)&s->mem[addr] & 3));
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cpu_to_le32w((uint32_t *)&s->mem[addr], val);
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}
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#if defined(DEBUG_EEPRO100)
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static const char *nic_dump(const uint8_t * buf, unsigned size)
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{
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@ -599,8 +655,7 @@ static void nic_selective_reset(EEPRO100State * s)
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TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
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memset(s->mem, 0, sizeof(s->mem));
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uint32_t val = BIT(21);
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memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
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e100_write_reg4(s, SCBCtrlMDI, BIT(21));
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assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
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memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
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@ -704,13 +759,13 @@ static void dump_statistics(EEPRO100State * s)
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* Number of data should check configuration!!!
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*/
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cpu_physical_memory_write(s->statsaddr, &s->statistics, s->stats_size);
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stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
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stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
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stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
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stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
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e100_stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
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e100_stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
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e100_stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
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e100_stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
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#if 0
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stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
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stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
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e100_stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
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e100_stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
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missing("CU dump statistical counters");
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#endif
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}
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@ -747,10 +802,10 @@ static void tx_command(EEPRO100State *s)
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}
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assert(tcb_bytes <= sizeof(buf));
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while (size < tcb_bytes) {
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uint32_t tx_buffer_address = ldl_phys(tbd_address);
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uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
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uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
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uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
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#if 0
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uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
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uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
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#endif
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tbd_address += 8;
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TRACE(RXTX, logout
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@ -769,9 +824,9 @@ static void tx_command(EEPRO100State *s)
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if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
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/* Extended Flexible TCB. */
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for (; tbd_count < 2; tbd_count++) {
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uint32_t tx_buffer_address = ldl_phys(tbd_address);
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uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
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uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
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uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
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uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
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uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
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tbd_address += 8;
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TRACE(RXTX, logout
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("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
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@ -787,9 +842,9 @@ static void tx_command(EEPRO100State *s)
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}
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tbd_address = tbd_array;
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for (; tbd_count < s->tx.tbd_count; tbd_count++) {
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uint32_t tx_buffer_address = ldl_phys(tbd_address);
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uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
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uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
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uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
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uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
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uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
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tbd_address += 8;
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TRACE(RXTX, logout
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("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
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@ -897,7 +952,7 @@ static void action_command(EEPRO100State *s)
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break;
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}
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/* Write new status. */
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stw_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
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e100_stw_le_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
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if (bit_i) {
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/* CU completed action. */
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eepro100_cx_interrupt(s);
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@ -964,7 +1019,7 @@ static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
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/* Dump statistical counters. */
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TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
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dump_statistics(s);
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stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
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e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
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break;
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case CU_CMD_BASE:
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/* Load CU base. */
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@ -975,7 +1030,7 @@ static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
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/* Dump and reset statistical counters. */
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TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
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dump_statistics(s);
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stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
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e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
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memset(&s->statistics, 0, sizeof(s->statistics));
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break;
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case CU_SRESUME:
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@ -1058,8 +1113,7 @@ static void eepro100_write_command(EEPRO100State * s, uint8_t val)
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static uint16_t eepro100_read_eeprom(EEPRO100State * s)
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{
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uint16_t val;
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memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
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uint16_t val = e100_read_reg2(s, SCBeeprom);
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if (eeprom93xx_read(s->eeprom)) {
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val |= EEPROM_DO;
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} else {
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@ -1129,8 +1183,7 @@ static const char *reg2name(uint8_t reg)
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static uint32_t eepro100_read_mdi(EEPRO100State * s)
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{
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uint32_t val;
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memcpy(&val, &s->mem[0x10], sizeof(val));
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uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
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#ifdef DEBUG_EEPRO100
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uint8_t raiseint = (val & BIT(29)) >> 29;
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@ -1239,7 +1292,7 @@ static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
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}
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}
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val = (val & 0xffff0000) + data;
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memcpy(&s->mem[0x10], &val, sizeof(val));
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e100_write_reg4(s, SCBCtrlMDI, val);
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}
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/*****************************************************************************
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@ -1266,7 +1319,6 @@ static uint32_t eepro100_read_port(EEPRO100State * s)
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static void eepro100_write_port(EEPRO100State * s, uint32_t val)
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{
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val = le32_to_cpu(val);
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uint32_t address = (val & ~PORT_SELECTION_MASK);
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uint8_t selection = (val & PORT_SELECTION_MASK);
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switch (selection) {
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@ -1301,7 +1353,7 @@ static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
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{
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uint8_t val = 0;
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if (addr <= sizeof(s->mem) - sizeof(val)) {
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memcpy(&val, &s->mem[addr], sizeof(val));
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val = s->mem[addr];
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}
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switch (addr) {
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@ -1344,7 +1396,7 @@ static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
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{
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uint16_t val = 0;
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if (addr <= sizeof(s->mem) - sizeof(val)) {
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memcpy(&val, &s->mem[addr], sizeof(val));
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val = e100_read_reg2(s, addr);
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}
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switch (addr) {
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@ -1367,7 +1419,7 @@ static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
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{
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uint32_t val = 0;
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if (addr <= sizeof(s->mem) - sizeof(val)) {
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memcpy(&val, &s->mem[addr], sizeof(val));
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val = e100_read_reg4(s, addr);
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}
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switch (addr) {
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@ -1398,7 +1450,7 @@ static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
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{
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/* SCBStatus is readonly. */
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if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
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memcpy(&s->mem[addr], &val, sizeof(val));
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s->mem[addr] = val;
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}
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switch (addr) {
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@ -1441,7 +1493,7 @@ static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
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{
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/* SCBStatus is readonly. */
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if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
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memcpy(&s->mem[addr], &val, sizeof(val));
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e100_write_reg2(s, addr, val);
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}
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switch (addr) {
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@ -1468,7 +1520,7 @@ static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
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static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
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{
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if (addr <= sizeof(s->mem) - sizeof(val)) {
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memcpy(&s->mem[addr], &val, sizeof(val));
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e100_write_reg4(s, addr, val);
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}
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switch (addr) {
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@ -1760,9 +1812,10 @@ static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size
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#endif
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TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
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rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
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stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
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rfd_status);
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stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
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e100_stw_le_phys(s->ru_base + s->ru_offset +
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offsetof(eepro100_rx_t, status), rfd_status);
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e100_stw_le_phys(s->ru_base + s->ru_offset +
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offsetof(eepro100_rx_t, count), size);
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/* Early receive interrupt not supported. */
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#if 0
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eepro100_er_interrupt(s);
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@ -1891,7 +1944,7 @@ static int e100_nic_init(PCIDevice *pci_dev)
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/* Handler for memory-mapped I/O */
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s->mmio_index =
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cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s,
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DEVICE_NATIVE_ENDIAN);
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DEVICE_LITTLE_ENDIAN);
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pci_register_bar_simple(&s->dev, 0, PCI_MEM_SIZE,
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PCI_BASE_ADDRESS_MEM_PREFETCH, s->mmio_index);
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