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target/mips: Move MXU_EN check one level higher

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Move MXU_EN check to the main MXU decoding function, to avoid code
repetition.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Aleksandar Markovic 2018-10-24 13:06:36 +02:00
parent 4ca837218c
commit e5bf8a0829
1 changed files with 238 additions and 271 deletions
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509
target/mips/translate.c
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@ -24095,23 +24095,16 @@ static void gen_mxu_s32m2i(DisasContext *ctx)
static void gen_mxu_s8ldd(DisasContext *ctx) static void gen_mxu_s8ldd(DisasContext *ctx)
{ {
TCGv t0, t1; TCGv t0, t1;
TCGLabel *l0;
uint32_t XRa, Rb, s8, optn3; uint32_t XRa, Rb, s8, optn3;
t0 = tcg_temp_new(); t0 = tcg_temp_new();
t1 = tcg_temp_new(); t1 = tcg_temp_new();
l0 = gen_new_label();
XRa = extract32(ctx->opcode, 6, 4); XRa = extract32(ctx->opcode, 6, 4);
s8 = extract32(ctx->opcode, 10, 8); s8 = extract32(ctx->opcode, 10, 8);
optn3 = extract32(ctx->opcode, 18, 3); optn3 = extract32(ctx->opcode, 18, 3);
Rb = extract32(ctx->opcode, 21, 5); Rb = extract32(ctx->opcode, 21, 5);
gen_load_mxu_cr(t0);
tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
gen_load_gpr(t0, Rb); gen_load_gpr(t0, Rb);
tcg_gen_addi_tl(t0, t0, (int8_t)s8); tcg_gen_addi_tl(t0, t0, (int8_t)s8);
@ -24169,8 +24162,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx)
gen_store_mxu_gpr(t0, XRa); gen_store_mxu_gpr(t0, XRa);
gen_set_label(l0);
tcg_temp_free(t0); tcg_temp_free(t0);
tcg_temp_free(t1); tcg_temp_free(t1);
} }
@ -24181,7 +24172,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx)
static void gen_mxu_d16mul(DisasContext *ctx) static void gen_mxu_d16mul(DisasContext *ctx)
{ {
TCGv t0, t1, t2, t3; TCGv t0, t1, t2, t3;
TCGLabel *l0;
uint32_t XRa, XRb, XRc, XRd, optn2; uint32_t XRa, XRb, XRc, XRd, optn2;
t0 = tcg_temp_new(); t0 = tcg_temp_new();
@ -24189,18 +24179,12 @@ static void gen_mxu_d16mul(DisasContext *ctx)
t2 = tcg_temp_new(); t2 = tcg_temp_new();
t3 = tcg_temp_new(); t3 = tcg_temp_new();
l0 = gen_new_label();
XRa = extract32(ctx->opcode, 6, 4); XRa = extract32(ctx->opcode, 6, 4);
XRb = extract32(ctx->opcode, 10, 4); XRb = extract32(ctx->opcode, 10, 4);
XRc = extract32(ctx->opcode, 14, 4); XRc = extract32(ctx->opcode, 14, 4);
XRd = extract32(ctx->opcode, 18, 4); XRd = extract32(ctx->opcode, 18, 4);
optn2 = extract32(ctx->opcode, 22, 2); optn2 = extract32(ctx->opcode, 22, 2);
gen_load_mxu_cr(t0);
tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
gen_load_mxu_gpr(t1, XRb); gen_load_mxu_gpr(t1, XRb);
tcg_gen_sextract_tl(t0, t1, 0, 16); tcg_gen_sextract_tl(t0, t1, 0, 16);
tcg_gen_sextract_tl(t1, t1, 16, 16); tcg_gen_sextract_tl(t1, t1, 16, 16);
@ -24229,8 +24213,6 @@ static void gen_mxu_d16mul(DisasContext *ctx)
gen_store_mxu_gpr(t3, XRa); gen_store_mxu_gpr(t3, XRa);
gen_store_mxu_gpr(t2, XRd); gen_store_mxu_gpr(t2, XRd);
gen_set_label(l0);
tcg_temp_free(t0); tcg_temp_free(t0);
tcg_temp_free(t1); tcg_temp_free(t1);
tcg_temp_free(t2); tcg_temp_free(t2);
@ -24244,7 +24226,6 @@ static void gen_mxu_d16mul(DisasContext *ctx)
static void gen_mxu_d16mac(DisasContext *ctx) static void gen_mxu_d16mac(DisasContext *ctx)
{ {
TCGv t0, t1, t2, t3; TCGv t0, t1, t2, t3;
TCGLabel *l0;
uint32_t XRa, XRb, XRc, XRd, optn2, aptn2; uint32_t XRa, XRb, XRc, XRd, optn2, aptn2;
t0 = tcg_temp_new(); t0 = tcg_temp_new();
@ -24252,8 +24233,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
t2 = tcg_temp_new(); t2 = tcg_temp_new();
t3 = tcg_temp_new(); t3 = tcg_temp_new();
l0 = gen_new_label();
XRa = extract32(ctx->opcode, 6, 4); XRa = extract32(ctx->opcode, 6, 4);
XRb = extract32(ctx->opcode, 10, 4); XRb = extract32(ctx->opcode, 10, 4);
XRc = extract32(ctx->opcode, 14, 4); XRc = extract32(ctx->opcode, 14, 4);
@ -24261,10 +24240,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
optn2 = extract32(ctx->opcode, 22, 2); optn2 = extract32(ctx->opcode, 22, 2);
aptn2 = extract32(ctx->opcode, 24, 2); aptn2 = extract32(ctx->opcode, 24, 2);
gen_load_mxu_cr(t0);
tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
gen_load_mxu_gpr(t1, XRb); gen_load_mxu_gpr(t1, XRb);
tcg_gen_sextract_tl(t0, t1, 0, 16); tcg_gen_sextract_tl(t0, t1, 0, 16);
tcg_gen_sextract_tl(t1, t1, 16, 16); tcg_gen_sextract_tl(t1, t1, 16, 16);
@ -24315,8 +24290,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
gen_store_mxu_gpr(t3, XRa); gen_store_mxu_gpr(t3, XRa);
gen_store_mxu_gpr(t2, XRd); gen_store_mxu_gpr(t2, XRd);
gen_set_label(l0);
tcg_temp_free(t0); tcg_temp_free(t0);
tcg_temp_free(t1); tcg_temp_free(t1);
tcg_temp_free(t2); tcg_temp_free(t2);
@ -24330,7 +24303,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
{ {
TCGv t0, t1, t2, t3, t4, t5, t6, t7; TCGv t0, t1, t2, t3, t4, t5, t6, t7;
TCGLabel *l0;
uint32_t XRa, XRb, XRc, XRd, sel; uint32_t XRa, XRb, XRc, XRd, sel;
t0 = tcg_temp_new(); t0 = tcg_temp_new();
@ -24342,18 +24314,12 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
t6 = tcg_temp_new(); t6 = tcg_temp_new();
t7 = tcg_temp_new(); t7 = tcg_temp_new();
l0 = gen_new_label();
XRa = extract32(ctx->opcode, 6, 4); XRa = extract32(ctx->opcode, 6, 4);
XRb = extract32(ctx->opcode, 10, 4); XRb = extract32(ctx->opcode, 10, 4);
XRc = extract32(ctx->opcode, 14, 4); XRc = extract32(ctx->opcode, 14, 4);
XRd = extract32(ctx->opcode, 18, 4); XRd = extract32(ctx->opcode, 18, 4);
sel = extract32(ctx->opcode, 22, 2); sel = extract32(ctx->opcode, 22, 2);
gen_load_mxu_cr(t0);
tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
gen_load_mxu_gpr(t3, XRb); gen_load_mxu_gpr(t3, XRb);
gen_load_mxu_gpr(t7, XRc); gen_load_mxu_gpr(t7, XRc);
@ -24404,8 +24370,6 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
gen_store_mxu_gpr(t0, XRd); gen_store_mxu_gpr(t0, XRd);
gen_store_mxu_gpr(t1, XRa); gen_store_mxu_gpr(t1, XRa);
gen_set_label(l0);
tcg_temp_free(t0); tcg_temp_free(t0);
tcg_temp_free(t1); tcg_temp_free(t1);
tcg_temp_free(t2); tcg_temp_free(t2);
@ -24423,23 +24387,16 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
{ {
TCGv t0, t1; TCGv t0, t1;
TCGLabel *l0;
uint32_t XRa, Rb, s12, sel; uint32_t XRa, Rb, s12, sel;
t0 = tcg_temp_new(); t0 = tcg_temp_new();
t1 = tcg_temp_new(); t1 = tcg_temp_new();
l0 = gen_new_label();
XRa = extract32(ctx->opcode, 6, 4); XRa = extract32(ctx->opcode, 6, 4);
s12 = extract32(ctx->opcode, 10, 10); s12 = extract32(ctx->opcode, 10, 10);
sel = extract32(ctx->opcode, 20, 1); sel = extract32(ctx->opcode, 20, 1);
Rb = extract32(ctx->opcode, 21, 5); Rb = extract32(ctx->opcode, 21, 5);
gen_load_mxu_cr(t0);
tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
gen_load_gpr(t0, Rb); gen_load_gpr(t0, Rb);
tcg_gen_movi_tl(t1, s12); tcg_gen_movi_tl(t1, s12);
@ -24456,8 +24413,6 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
} }
gen_store_mxu_gpr(t1, XRa); gen_store_mxu_gpr(t1, XRa);
gen_set_label(l0);
tcg_temp_free(t0); tcg_temp_free(t0);
tcg_temp_free(t1); tcg_temp_free(t1);
} }
@ -25383,232 +25338,244 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
return; return;
} }
switch (opcode) { {
case OPC_MXU_S32MADD: TCGv t_mxu_cr = tcg_temp_new();
/* TODO: Implement emulation of S32MADD instruction. */ TCGLabel *l_exit = gen_new_label();
MIPS_INVAL("OPC_MXU_S32MADD");
generate_exception_end(ctx, EXCP_RI); gen_load_mxu_cr(t_mxu_cr);
break; tcg_gen_andi_tl(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN);
case OPC_MXU_S32MADDU: tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit);
/* TODO: Implement emulation of S32MADDU instruction. */
MIPS_INVAL("OPC_MXU_S32MADDU"); switch (opcode) {
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_S32MADD:
break; /* TODO: Implement emulation of S32MADD instruction. */
case OPC_MXU__POOL00: MIPS_INVAL("OPC_MXU_S32MADD");
decode_opc_mxu__pool00(env, ctx); generate_exception_end(ctx, EXCP_RI);
break; break;
case OPC_MXU_S32MSUB: case OPC_MXU_S32MADDU:
/* TODO: Implement emulation of S32MSUB instruction. */ /* TODO: Implement emulation of S32MADDU instruction. */
MIPS_INVAL("OPC_MXU_S32MSUB"); MIPS_INVAL("OPC_MXU_S32MADDU");
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
break; break;
case OPC_MXU_S32MSUBU: case OPC_MXU__POOL00:
/* TODO: Implement emulation of S32MSUBU instruction. */ decode_opc_mxu__pool00(env, ctx);
MIPS_INVAL("OPC_MXU_S32MSUBU"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_S32MSUB:
break; /* TODO: Implement emulation of S32MSUB instruction. */
case OPC_MXU__POOL01: MIPS_INVAL("OPC_MXU_S32MSUB");
decode_opc_mxu__pool01(env, ctx); generate_exception_end(ctx, EXCP_RI);
break; break;
case OPC_MXU__POOL02: case OPC_MXU_S32MSUBU:
decode_opc_mxu__pool02(env, ctx); /* TODO: Implement emulation of S32MSUBU instruction. */
break; MIPS_INVAL("OPC_MXU_S32MSUBU");
case OPC_MXU_D16MUL: generate_exception_end(ctx, EXCP_RI);
gen_mxu_d16mul(ctx); break;
break; case OPC_MXU__POOL01:
case OPC_MXU__POOL03: decode_opc_mxu__pool01(env, ctx);
decode_opc_mxu__pool03(env, ctx); break;
break; case OPC_MXU__POOL02:
case OPC_MXU_D16MAC: decode_opc_mxu__pool02(env, ctx);
gen_mxu_d16mac(ctx); break;
break; case OPC_MXU_D16MUL:
case OPC_MXU_D16MACF: gen_mxu_d16mul(ctx);
/* TODO: Implement emulation of D16MACF instruction. */ break;
MIPS_INVAL("OPC_MXU_D16MACF"); case OPC_MXU__POOL03:
generate_exception_end(ctx, EXCP_RI); decode_opc_mxu__pool03(env, ctx);
break; break;
case OPC_MXU_D16MADL: case OPC_MXU_D16MAC:
/* TODO: Implement emulation of D16MADL instruction. */ gen_mxu_d16mac(ctx);
MIPS_INVAL("OPC_MXU_D16MADL"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_D16MACF:
break; /* TODO: Implement emulation of D16MACF instruction. */
case OPC_MXU_S16MAD: MIPS_INVAL("OPC_MXU_D16MACF");
/* TODO: Implement emulation of S16MAD instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_S16MAD"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_D16MADL:
break; /* TODO: Implement emulation of D16MADL instruction. */
case OPC_MXU_Q16ADD: MIPS_INVAL("OPC_MXU_D16MADL");
/* TODO: Implement emulation of Q16ADD instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_Q16ADD"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_S16MAD:
break; /* TODO: Implement emulation of S16MAD instruction. */
case OPC_MXU_D16MACE: MIPS_INVAL("OPC_MXU_S16MAD");
/* TODO: Implement emulation of D16MACE instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_D16MACE"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_Q16ADD:
break; /* TODO: Implement emulation of Q16ADD instruction. */
case OPC_MXU__POOL04: MIPS_INVAL("OPC_MXU_Q16ADD");
decode_opc_mxu__pool04(env, ctx); generate_exception_end(ctx, EXCP_RI);
break; break;
case OPC_MXU__POOL05: case OPC_MXU_D16MACE:
decode_opc_mxu__pool05(env, ctx); /* TODO: Implement emulation of D16MACE instruction. */
break; MIPS_INVAL("OPC_MXU_D16MACE");
case OPC_MXU__POOL06: generate_exception_end(ctx, EXCP_RI);
decode_opc_mxu__pool06(env, ctx); break;
break; case OPC_MXU__POOL04:
case OPC_MXU__POOL07: decode_opc_mxu__pool04(env, ctx);
decode_opc_mxu__pool07(env, ctx); break;
break; case OPC_MXU__POOL05:
case OPC_MXU__POOL08: decode_opc_mxu__pool05(env, ctx);
decode_opc_mxu__pool08(env, ctx); break;
break; case OPC_MXU__POOL06:
case OPC_MXU__POOL09: decode_opc_mxu__pool06(env, ctx);
decode_opc_mxu__pool09(env, ctx); break;
break; case OPC_MXU__POOL07:
case OPC_MXU__POOL10: decode_opc_mxu__pool07(env, ctx);
decode_opc_mxu__pool10(env, ctx); break;
break; case OPC_MXU__POOL08:
case OPC_MXU__POOL11: decode_opc_mxu__pool08(env, ctx);
decode_opc_mxu__pool11(env, ctx); break;
break; case OPC_MXU__POOL09:
case OPC_MXU_D32ADD: decode_opc_mxu__pool09(env, ctx);
/* TODO: Implement emulation of D32ADD instruction. */ break;
MIPS_INVAL("OPC_MXU_D32ADD"); case OPC_MXU__POOL10:
generate_exception_end(ctx, EXCP_RI); decode_opc_mxu__pool10(env, ctx);
break; break;
case OPC_MXU__POOL12: case OPC_MXU__POOL11:
decode_opc_mxu__pool12(env, ctx); decode_opc_mxu__pool11(env, ctx);
break; break;
case OPC_MXU__POOL13: case OPC_MXU_D32ADD:
decode_opc_mxu__pool13(env, ctx); /* TODO: Implement emulation of D32ADD instruction. */
break; MIPS_INVAL("OPC_MXU_D32ADD");
case OPC_MXU__POOL14: generate_exception_end(ctx, EXCP_RI);
decode_opc_mxu__pool14(env, ctx); break;
break; case OPC_MXU__POOL12:
case OPC_MXU_Q8ACCE: decode_opc_mxu__pool12(env, ctx);
/* TODO: Implement emulation of Q8ACCE instruction. */ break;
MIPS_INVAL("OPC_MXU_Q8ACCE"); case OPC_MXU__POOL13:
generate_exception_end(ctx, EXCP_RI); decode_opc_mxu__pool13(env, ctx);
break; break;
case OPC_MXU_S8LDD: case OPC_MXU__POOL14:
gen_mxu_s8ldd(ctx); decode_opc_mxu__pool14(env, ctx);
break; break;
case OPC_MXU_S8STD: case OPC_MXU_Q8ACCE:
/* TODO: Implement emulation of S8STD instruction. */ /* TODO: Implement emulation of Q8ACCE instruction. */
MIPS_INVAL("OPC_MXU_S8STD"); MIPS_INVAL("OPC_MXU_Q8ACCE");
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
break; break;
case OPC_MXU_S8LDI: case OPC_MXU_S8LDD:
/* TODO: Implement emulation of S8LDI instruction. */ gen_mxu_s8ldd(ctx);
MIPS_INVAL("OPC_MXU_S8LDI"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_S8STD:
break; /* TODO: Implement emulation of S8STD instruction. */
case OPC_MXU_S8SDI: MIPS_INVAL("OPC_MXU_S8STD");
/* TODO: Implement emulation of S8SDI instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_S8SDI"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_S8LDI:
break; /* TODO: Implement emulation of S8LDI instruction. */
case OPC_MXU__POOL15: MIPS_INVAL("OPC_MXU_S8LDI");
decode_opc_mxu__pool15(env, ctx); generate_exception_end(ctx, EXCP_RI);
break; break;
case OPC_MXU__POOL16: case OPC_MXU_S8SDI:
decode_opc_mxu__pool16(env, ctx); /* TODO: Implement emulation of S8SDI instruction. */
break; MIPS_INVAL("OPC_MXU_S8SDI");
case OPC_MXU_LXB: generate_exception_end(ctx, EXCP_RI);
/* TODO: Implement emulation of LXB instruction. */ break;
MIPS_INVAL("OPC_MXU_LXB"); case OPC_MXU__POOL15:
generate_exception_end(ctx, EXCP_RI); decode_opc_mxu__pool15(env, ctx);
break; break;
case OPC_MXU_S16LDD: case OPC_MXU__POOL16:
/* TODO: Implement emulation of S16LDD instruction. */ decode_opc_mxu__pool16(env, ctx);
MIPS_INVAL("OPC_MXU_S16LDD"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_LXB:
break; /* TODO: Implement emulation of LXB instruction. */
case OPC_MXU_S16STD: MIPS_INVAL("OPC_MXU_LXB");
/* TODO: Implement emulation of S16STD instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_S16STD"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_S16LDD:
break; /* TODO: Implement emulation of S16LDD instruction. */
case OPC_MXU_S16LDI: MIPS_INVAL("OPC_MXU_S16LDD");
/* TODO: Implement emulation of S16LDI instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_S16LDI"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_S16STD:
break; /* TODO: Implement emulation of S16STD instruction. */
case OPC_MXU_S16SDI: MIPS_INVAL("OPC_MXU_S16STD");
/* TODO: Implement emulation of S16SDI instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_S16SDI"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_S16LDI:
break; /* TODO: Implement emulation of S16LDI instruction. */
case OPC_MXU_D32SLL: MIPS_INVAL("OPC_MXU_S16LDI");
/* TODO: Implement emulation of D32SLL instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_D32SLL"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_S16SDI:
break; /* TODO: Implement emulation of S16SDI instruction. */
case OPC_MXU_D32SLR: MIPS_INVAL("OPC_MXU_S16SDI");
/* TODO: Implement emulation of D32SLR instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_D32SLR"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_D32SLL:
break; /* TODO: Implement emulation of D32SLL instruction. */
case OPC_MXU_D32SARL: MIPS_INVAL("OPC_MXU_D32SLL");
/* TODO: Implement emulation of D32SARL instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_D32SARL"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_D32SLR:
break; /* TODO: Implement emulation of D32SLR instruction. */
case OPC_MXU_D32SAR: MIPS_INVAL("OPC_MXU_D32SLR");
/* TODO: Implement emulation of D32SAR instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_D32SAR"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_D32SARL:
break; /* TODO: Implement emulation of D32SARL instruction. */
case OPC_MXU_Q16SLL: MIPS_INVAL("OPC_MXU_D32SARL");
/* TODO: Implement emulation of Q16SLL instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_Q16SLL"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_D32SAR:
break; /* TODO: Implement emulation of D32SAR instruction. */
case OPC_MXU_Q16SLR: MIPS_INVAL("OPC_MXU_D32SAR");
/* TODO: Implement emulation of Q16SLR instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_Q16SLR"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_Q16SLL:
break; /* TODO: Implement emulation of Q16SLL instruction. */
case OPC_MXU__POOL17: MIPS_INVAL("OPC_MXU_Q16SLL");
decode_opc_mxu__pool17(env, ctx); generate_exception_end(ctx, EXCP_RI);
break; break;
case OPC_MXU_Q16SAR: case OPC_MXU_Q16SLR:
/* TODO: Implement emulation of Q16SAR instruction. */ /* TODO: Implement emulation of Q16SLR instruction. */
MIPS_INVAL("OPC_MXU_Q16SAR"); MIPS_INVAL("OPC_MXU_Q16SLR");
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
break; break;
case OPC_MXU__POOL18: case OPC_MXU__POOL17:
decode_opc_mxu__pool18(env, ctx); decode_opc_mxu__pool17(env, ctx);
break; break;
case OPC_MXU__POOL19: case OPC_MXU_Q16SAR:
decode_opc_mxu__pool19(env, ctx); /* TODO: Implement emulation of Q16SAR instruction. */
break; MIPS_INVAL("OPC_MXU_Q16SAR");
case OPC_MXU__POOL20: generate_exception_end(ctx, EXCP_RI);
decode_opc_mxu__pool20(env, ctx); break;
break; case OPC_MXU__POOL18:
case OPC_MXU_Q16SCOP: decode_opc_mxu__pool18(env, ctx);
/* TODO: Implement emulation of Q16SCOP instruction. */ break;
MIPS_INVAL("OPC_MXU_Q16SCOP"); case OPC_MXU__POOL19:
generate_exception_end(ctx, EXCP_RI); decode_opc_mxu__pool19(env, ctx);
break; break;
case OPC_MXU_Q8MADL: case OPC_MXU__POOL20:
/* TODO: Implement emulation of Q8MADL instruction. */ decode_opc_mxu__pool20(env, ctx);
MIPS_INVAL("OPC_MXU_Q8MADL"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_Q16SCOP:
break; /* TODO: Implement emulation of Q16SCOP instruction. */
case OPC_MXU_S32SFL: MIPS_INVAL("OPC_MXU_Q16SCOP");
/* TODO: Implement emulation of S32SFL instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_S32SFL"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_Q8MADL:
break; /* TODO: Implement emulation of Q8MADL instruction. */
case OPC_MXU_Q8SAD: MIPS_INVAL("OPC_MXU_Q8MADL");
/* TODO: Implement emulation of Q8SAD instruction. */ generate_exception_end(ctx, EXCP_RI);
MIPS_INVAL("OPC_MXU_Q8SAD"); break;
generate_exception_end(ctx, EXCP_RI); case OPC_MXU_S32SFL:
break; /* TODO: Implement emulation of S32SFL instruction. */
default: MIPS_INVAL("OPC_MXU_S32SFL");
MIPS_INVAL("decode_opc_mxu"); generate_exception_end(ctx, EXCP_RI);
generate_exception_end(ctx, EXCP_RI); break;
case OPC_MXU_Q8SAD:
/* TODO: Implement emulation of Q8SAD instruction. */
MIPS_INVAL("OPC_MXU_Q8SAD");
generate_exception_end(ctx, EXCP_RI);
break;
default:
MIPS_INVAL("decode_opc_mxu");
generate_exception_end(ctx, EXCP_RI);
}
gen_set_label(l_exit);
tcg_temp_free(t_mxu_cr);
} }
} }