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More cache tuning fixes:

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* fix the tunable cache line size probe for PowerPC 970.
* initialize HID5 so cache line is 32 bytes long when running in user-mode only


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3322 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-10-04 01:50:03 +00:00
parent d63001d114
commit e57448f11c
2 changed files with 23 additions and 3 deletions
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2
target-ppc/op_helper_mem.h
View File

@ -324,7 +324,7 @@ void glue(do_dcbz_64, MEMSUFFIX) (void)
int dcache_line_size = env->dcache_line_size;
/* XXX: should be 970 specific (?) */
if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
if (((env->spr[SPR_970_HID5] >> 6) & 0x3) == 0x2)
dcache_line_size = 32;
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);

24
target-ppc/translate_init.c
View File

@ -4063,6 +4063,16 @@ static void init_proc_970 (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
spr_register(env, SPR_970_HID5, "HID5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
#if defined(CONFIG_USER_ONLY)
0x00000080
#else
0x00000000
#endif
);
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
@ -4116,7 +4126,12 @@ static void init_proc_970FX (CPUPPCState *env)
spr_register(env, SPR_970_HID5, "HID5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
#if defined(CONFIG_USER_ONLY)
0x00000080
#else
0x00000000
#endif
);
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
@ -4170,7 +4185,12 @@ static void init_proc_970GX (CPUPPCState *env)
spr_register(env, SPR_970_HID5, "HID5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
#if defined(CONFIG_USER_ONLY)
0x00000080
#else
0x00000000
#endif
);
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);