iommu: Introduce IOMMU emulation infrastructure
This patch adds the basic infrastructure necessary to emulate an IOMMU visible to the guest. The DMAContext structure is extended with information and a callback describing the translation, and the various DMA functions used by devices will now perform IOMMU translation using this callback. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduard - Gabriel Munteanu <eduard.munteanu@linux360.ro> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
David Gibson
Anthony Liguori
parent
e2f89926f1
commit
e5332e6334
172
dma-helpers.c
172
dma-helpers.c
@ -9,8 +9,12 @@
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#include "dma.h"
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#include "trace.h"
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#include "range.h"
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#include "qemu-thread.h"
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int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len)
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/* #define DEBUG_IOMMU */
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static void do_dma_memory_set(dma_addr_t addr, uint8_t c, dma_addr_t len)
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{
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#define FILLBUF_SIZE 512
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uint8_t fillbuf[FILLBUF_SIZE];
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@ -23,6 +27,15 @@ int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len)
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len -= len;
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addr += len;
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}
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}
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int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len)
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{
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if (dma_has_iommu(dma)) {
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return iommu_dma_memory_set(dma, addr, c, len);
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}
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do_dma_memory_set(addr, c, len);
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return 0;
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}
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@ -260,3 +273,160 @@ void dma_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie,
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{
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bdrv_acct_start(bs, cookie, sg->size, type);
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}
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bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
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DMADirection dir)
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{
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target_phys_addr_t paddr, plen;
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#ifdef DEBUG_IOMMU
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fprintf(stderr, "dma_memory_check context=%p addr=0x" DMA_ADDR_FMT
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" len=0x" DMA_ADDR_FMT " dir=%d\n", dma, addr, len, dir);
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#endif
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while (len) {
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if (dma->translate(dma, addr, &paddr, &plen, dir) != 0) {
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return false;
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}
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/* The translation might be valid for larger regions. */
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if (plen > len) {
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plen = len;
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}
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len -= plen;
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addr += plen;
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}
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return true;
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}
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int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
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void *buf, dma_addr_t len, DMADirection dir)
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{
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target_phys_addr_t paddr, plen;
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int err;
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#ifdef DEBUG_IOMMU
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fprintf(stderr, "dma_memory_rw context=%p addr=0x" DMA_ADDR_FMT " len=0x"
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DMA_ADDR_FMT " dir=%d\n", dma, addr, len, dir);
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#endif
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while (len) {
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err = dma->translate(dma, addr, &paddr, &plen, dir);
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if (err) {
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/*
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* In case of failure on reads from the guest, we clean the
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* destination buffer so that a device that doesn't test
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* for errors will not expose qemu internal memory.
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*/
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memset(buf, 0, len);
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return -1;
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}
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/* The translation might be valid for larger regions. */
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if (plen > len) {
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plen = len;
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}
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cpu_physical_memory_rw(paddr, buf, plen,
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dir == DMA_DIRECTION_FROM_DEVICE);
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len -= plen;
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addr += plen;
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buf += plen;
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}
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return 0;
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}
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int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c,
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dma_addr_t len)
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{
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target_phys_addr_t paddr, plen;
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int err;
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#ifdef DEBUG_IOMMU
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fprintf(stderr, "dma_memory_set context=%p addr=0x" DMA_ADDR_FMT
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" len=0x" DMA_ADDR_FMT "\n", dma, addr, len);
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#endif
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while (len) {
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err = dma->translate(dma, addr, &paddr, &plen,
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DMA_DIRECTION_FROM_DEVICE);
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if (err) {
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return err;
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}
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/* The translation might be valid for larger regions. */
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if (plen > len) {
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plen = len;
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}
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do_dma_memory_set(paddr, c, plen);
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len -= plen;
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addr += plen;
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}
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return 0;
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}
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void dma_context_init(DMAContext *dma, DMATranslateFunc translate,
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DMAMapFunc map, DMAUnmapFunc unmap)
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{
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#ifdef DEBUG_IOMMU
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fprintf(stderr, "dma_context_init(%p, %p, %p, %p)\n",
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dma, translate, map, unmap);
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#endif
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dma->translate = translate;
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dma->map = map;
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dma->unmap = unmap;
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}
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void *iommu_dma_memory_map(DMAContext *dma, dma_addr_t addr, dma_addr_t *len,
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DMADirection dir)
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{
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int err;
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target_phys_addr_t paddr, plen;
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void *buf;
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if (dma->map) {
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return dma->map(dma, addr, len, dir);
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}
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plen = *len;
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err = dma->translate(dma, addr, &paddr, &plen, dir);
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if (err) {
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return NULL;
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}
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/*
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* If this is true, the virtual region is contiguous,
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* but the translated physical region isn't. We just
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* clamp *len, much like cpu_physical_memory_map() does.
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*/
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if (plen < *len) {
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*len = plen;
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}
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buf = cpu_physical_memory_map(paddr, &plen,
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dir == DMA_DIRECTION_FROM_DEVICE);
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*len = plen;
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return buf;
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}
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void iommu_dma_memory_unmap(DMAContext *dma, void *buffer, dma_addr_t len,
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DMADirection dir, dma_addr_t access_len)
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{
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if (dma->unmap) {
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dma->unmap(dma, buffer, len, dir, access_len);
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return;
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}
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cpu_physical_memory_unmap(buffer, len,
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dir == DMA_DIRECTION_FROM_DEVICE,
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access_len);
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}
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106
dma.h
106
dma.h
@ -31,28 +31,74 @@ struct QEMUSGList {
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};
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#if defined(TARGET_PHYS_ADDR_BITS)
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typedef target_phys_addr_t dma_addr_t;
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#define DMA_ADDR_BITS TARGET_PHYS_ADDR_BITS
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#define DMA_ADDR_FMT TARGET_FMT_plx
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/*
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* When an IOMMU is present, bus addresses become distinct from
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* CPU/memory physical addresses and may be a different size. Because
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* the IOVA size depends more on the bus than on the platform, we more
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* or less have to treat these as 64-bit always to cover all (or at
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* least most) cases.
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*/
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typedef uint64_t dma_addr_t;
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#define DMA_ADDR_BITS 64
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#define DMA_ADDR_FMT "%" PRIx64
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typedef int DMATranslateFunc(DMAContext *dma,
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dma_addr_t addr,
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target_phys_addr_t *paddr,
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target_phys_addr_t *len,
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DMADirection dir);
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typedef void* DMAMapFunc(DMAContext *dma,
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dma_addr_t addr,
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dma_addr_t *len,
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DMADirection dir);
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typedef void DMAUnmapFunc(DMAContext *dma,
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void *buffer,
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dma_addr_t len,
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DMADirection dir,
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dma_addr_t access_len);
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struct DMAContext {
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DMATranslateFunc *translate;
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DMAMapFunc *map;
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DMAUnmapFunc *unmap;
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};
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static inline bool dma_has_iommu(DMAContext *dma)
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{
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return !!dma;
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}
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/* Checks that the given range of addresses is valid for DMA. This is
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* useful for certain cases, but usually you should just use
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* dma_memory_{read,write}() and check for errors */
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static inline bool dma_memory_valid(DMAContext *dma, dma_addr_t addr,
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dma_addr_t len, DMADirection dir)
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bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
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DMADirection dir);
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static inline bool dma_memory_valid(DMAContext *dma,
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dma_addr_t addr, dma_addr_t len,
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DMADirection dir)
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{
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/* Stub version, with no iommu we assume all bus addresses are valid */
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return true;
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if (!dma_has_iommu(dma)) {
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return true;
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} else {
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return iommu_dma_memory_valid(dma, addr, len, dir);
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}
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}
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int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
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void *buf, dma_addr_t len, DMADirection dir);
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static inline int dma_memory_rw(DMAContext *dma, dma_addr_t addr,
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void *buf, dma_addr_t len, DMADirection dir)
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{
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/* Stub version when we have no iommu support */
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cpu_physical_memory_rw(addr, buf, (target_phys_addr_t)len,
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dir == DMA_DIRECTION_FROM_DEVICE);
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return 0;
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if (!dma_has_iommu(dma)) {
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/* Fast-path for no IOMMU */
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cpu_physical_memory_rw(addr, buf, len,
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dir == DMA_DIRECTION_FROM_DEVICE);
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return 0;
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} else {
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return iommu_dma_memory_rw(dma, addr, buf, len, dir);
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}
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}
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static inline int dma_memory_read(DMAContext *dma, dma_addr_t addr,
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@ -68,28 +114,45 @@ static inline int dma_memory_write(DMAContext *dma, dma_addr_t addr,
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DMA_DIRECTION_FROM_DEVICE);
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}
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int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c,
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dma_addr_t len);
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int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len);
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void *iommu_dma_memory_map(DMAContext *dma,
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dma_addr_t addr, dma_addr_t *len,
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DMADirection dir);
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static inline void *dma_memory_map(DMAContext *dma,
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dma_addr_t addr, dma_addr_t *len,
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DMADirection dir)
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{
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target_phys_addr_t xlen = *len;
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void *p;
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if (!dma_has_iommu(dma)) {
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target_phys_addr_t xlen = *len;
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void *p;
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p = cpu_physical_memory_map(addr, &xlen,
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dir == DMA_DIRECTION_FROM_DEVICE);
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*len = xlen;
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return p;
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p = cpu_physical_memory_map(addr, &xlen,
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dir == DMA_DIRECTION_FROM_DEVICE);
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*len = xlen;
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return p;
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} else {
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return iommu_dma_memory_map(dma, addr, len, dir);
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}
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}
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void iommu_dma_memory_unmap(DMAContext *dma,
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void *buffer, dma_addr_t len,
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DMADirection dir, dma_addr_t access_len);
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static inline void dma_memory_unmap(DMAContext *dma,
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void *buffer, dma_addr_t len,
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DMADirection dir, dma_addr_t access_len)
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{
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return cpu_physical_memory_unmap(buffer, (target_phys_addr_t)len,
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dir == DMA_DIRECTION_FROM_DEVICE,
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access_len);
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if (!dma_has_iommu(dma)) {
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return cpu_physical_memory_unmap(buffer, (target_phys_addr_t)len,
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dir == DMA_DIRECTION_FROM_DEVICE,
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access_len);
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} else {
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iommu_dma_memory_unmap(dma, buffer, len, dir, access_len);
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}
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}
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#define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \
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@ -130,6 +193,9 @@ DEFINE_LDST_DMA(q, q, 64, be);
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#undef DEFINE_LDST_DMA
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void dma_context_init(DMAContext *dma, DMATranslateFunc translate,
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DMAMapFunc map, DMAUnmapFunc unmap);
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struct ScatterGatherEntry {
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dma_addr_t base;
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dma_addr_t len;
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@ -6,7 +6,5 @@
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qdev-addr.h"
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#define DEFINE_PROP_DMAADDR(_n, _s, _f, _d) \
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DEFINE_PROP_TADDR(_n, _s, _f, _d)
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DEFINE_PROP_HEX64(_n, _s, _f, _d)
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