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hw/isa/piix3: Create IDE controller in host device

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The IDE controller is an integral part of PIIX3 (function 1). So create it as
part of the south bridge.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-12-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Bernhard Beschow 2023-10-07 14:38:19 +02:00 committed by Michael S. Tsirkin
parent 56b1f50e3c
commit e47e5a5b79
5 changed files with 18 additions and 8 deletions
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1
hw/i386/Kconfig
View File

@ -73,7 +73,6 @@ config I440FX
select PC_ACPI
select PCI_I440FX
select PIIX3
select IDE_PIIX
select DIMM
select SMBIOS
select FW_CFG_DMA

13
hw/i386/pc_piix.c
View File

@ -43,7 +43,6 @@
#include "net/net.h"
#include "hw/ide/isa.h"
#include "hw/ide/pci.h"
#include "hw/ide/piix.h"
#include "hw/irq.h"
#include "sysemu/kvm.h"
#include "hw/i386/kvm/clock.h"
@ -290,6 +289,10 @@ static void pc_init1(MachineState *machine,
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
"rtc"));
dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide"));
pci_ide_create_devs(PCI_DEVICE(dev));
idebus[0] = qdev_get_child_bus(dev, "ide.0");
idebus[1] = qdev_get_child_bus(dev, "ide.1");
} else {
isa_bus = isa_bus_new(NULL, system_memory, system_io,
&error_abort);
@ -301,6 +304,8 @@ static void pc_init1(MachineState *machine,
i8257_dma_init(isa_bus, 0);
pcms->hpet_enabled = false;
idebus[0] = NULL;
idebus[1] = NULL;
}
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
@ -329,12 +334,6 @@ static void pc_init1(MachineState *machine,
pc_nic_init(pcmc, isa_bus, pci_bus);
if (pcmc->pci_enabled) {
PCIDevice *dev;
dev = pci_create_simple(pci_bus, piix3_devfn + 1, TYPE_PIIX3_IDE);
pci_ide_create_devs(dev);
idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0");
idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1");
pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
}
#ifdef CONFIG_IDE_ISA

1
hw/isa/Kconfig
View File

@ -34,6 +34,7 @@ config PC87312
config PIIX3
bool
select I8257
select IDE_PIIX
select ISA_BUS
select MC146818RTC

9
hw/isa/piix3.c
View File

@ -29,6 +29,7 @@
#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/ide/piix.h"
#include "hw/isa/isa.h"
#include "sysemu/runstate.h"
#include "migration/vmstate.h"
@ -265,6 +266,7 @@ static const MemoryRegionOps rcr_ops = {
static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = PIIX3_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
uint32_t irq;
@ -290,6 +292,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
}
irq = object_property_get_uint(OBJECT(&d->rtc), "irq", &error_fatal);
isa_connect_gpio_out(ISA_DEVICE(&d->rtc), 0, irq);
/* IDE */
qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1);
if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) {
return;
}
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@ -321,6 +329,7 @@ static void pci_piix3_init(Object *obj)
ISA_NUM_IRQS);
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
}
static void pci_piix3_class_init(ObjectClass *klass, void *data)

2
include/hw/southbridge/piix.h
View File

@ -13,6 +13,7 @@
#define HW_SOUTHBRIDGE_PIIX_H
#include "hw/pci/pci_device.h"
#include "hw/ide/pci.h"
#include "hw/rtc/mc146818rtc.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
@ -52,6 +53,7 @@ struct PIIXState {
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
MC146818RtcState rtc;
PCIIDEState ide;
/* Reset Control Register contents */
uint8_t rcr;