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target/sparc: Use i128 for FSQRTq

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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-7-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-11-03 10:38:25 -07:00
parent daf457d40f
commit e41716be4d
3 changed files with 32 additions and 8 deletions
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26
target/sparc/fop_helper.c
View File

@ -26,6 +26,28 @@
#define QT0 (env->qt0)
#define QT1 (env->qt1)
static inline float128 f128_in(Int128 i)
{
union {
Int128 i;
float128 f;
} u;
u.i = i;
return u.f;
}
static inline Int128 f128_ret(float128 f)
{
union {
Int128 i;
float128 f;
} u;
u.f = f;
return u.i;
}
static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra)
{
target_ulong status = get_float_exception_flags(&env->fp_status);
@ -222,9 +244,9 @@ float64 helper_fsqrtd(CPUSPARCState *env, float64 src)
return float64_sqrt(src, &env->fp_status);
}
void helper_fsqrtq(CPUSPARCState *env)
Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src)
{
QT0 = float128_sqrt(QT1, &env->fp_status);
return f128_ret(float128_sqrt(f128_in(src), &env->fp_status));
}
#define GEN_FCMP(name, size, reg1, reg2, FS, E) \

2
target/sparc/helper.h
View File

@ -43,7 +43,7 @@ DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_RWG, i128, env, i128)
DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env)
#ifdef TARGET_SPARC64

12
target/sparc/translate.c
View File

@ -4669,8 +4669,10 @@ TRANS(FNEGq, 64, do_qq, a, gen_op_fnegq)
TRANS(FABSq, 64, do_qq, a, gen_op_fabsq)
static bool do_env_qq(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv_env))
void (*func)(TCGv_i128, TCGv_env, TCGv_i128))
{
TCGv_i128 t;
if (gen_trap_ifnofpu(dc)) {
return true;
}
@ -4679,11 +4681,11 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a,
}
gen_op_clear_ieee_excp_and_FTT();
gen_op_load_fpr_QT1(QFPREG(a->rs));
func(tcg_env);
t = gen_load_fpr_Q(dc, a->rs);
func(t, tcg_env, t);
gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_op_store_QT0_fpr(QFPREG(a->rd));
gen_update_fprs_dirty(dc, QFPREG(a->rd));
gen_store_fpr_Q(dc, a->rd, t);
return advance_pc(dc);
}