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correct split between helper.c and op_helper.c - cosmetics

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1505 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2005-07-04 22:17:33 +00:00
parent fdabc366bd
commit e37e863f5e
5 changed files with 233 additions and 242 deletions
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168
target-mips/cpu.h
View File

@ -240,174 +240,6 @@ enum {
EXCP_FLUSH = 0x109,
};
/* MIPS opcodes */
#define EXT_SPECIAL 0x100
#define EXT_SPECIAL2 0x200
#define EXT_REGIMM 0x300
#define EXT_CP0 0x400
#define EXT_CP1 0x500
#define EXT_CP2 0x600
#define EXT_CP3 0x700
enum {
/* indirect opcode tables */
OPC_SPECIAL = 0x00,
OPC_BREGIMM = 0x01,
OPC_CP0 = 0x10,
OPC_CP1 = 0x11,
OPC_CP2 = 0x12,
OPC_CP3 = 0x13,
OPC_SPECIAL2 = 0x1C,
/* arithmetic with immediate */
OPC_ADDI = 0x08,
OPC_ADDIU = 0x09,
OPC_SLTI = 0x0A,
OPC_SLTIU = 0x0B,
OPC_ANDI = 0x0C,
OPC_ORI = 0x0D,
OPC_XORI = 0x0E,
OPC_LUI = 0x0F,
/* Jump and branches */
OPC_J = 0x02,
OPC_JAL = 0x03,
OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */
OPC_BEQL = 0x14,
OPC_BNE = 0x05,
OPC_BNEL = 0x15,
OPC_BLEZ = 0x06,
OPC_BLEZL = 0x16,
OPC_BGTZ = 0x07,
OPC_BGTZL = 0x17,
OPC_JALX = 0x1D, /* MIPS 16 only */
/* Load and stores */
OPC_LB = 0x20,
OPC_LH = 0x21,
OPC_LWL = 0x22,
OPC_LW = 0x23,
OPC_LBU = 0x24,
OPC_LHU = 0x25,
OPC_LWR = 0x26,
OPC_SB = 0x28,
OPC_SH = 0x29,
OPC_SWL = 0x2A,
OPC_SW = 0x2B,
OPC_SWR = 0x2E,
OPC_LL = 0x30,
OPC_SC = 0x38,
/* Floating point load/store */
OPC_LWC1 = 0x31,
OPC_LWC2 = 0x32,
OPC_LDC1 = 0x35,
OPC_LDC2 = 0x36,
OPC_SWC1 = 0x39,
OPC_SWC2 = 0x3A,
OPC_SDC1 = 0x3D,
OPC_SDC2 = 0x3E,
/* Cache and prefetch */
OPC_CACHE = 0x2F,
OPC_PREF = 0x33,
};
/* MIPS special opcodes */
enum {
/* Shifts */
OPC_SLL = 0x00 | EXT_SPECIAL,
/* NOP is SLL r0, r0, 0 */
/* SSNOP is SLL r0, r0, 1 */
OPC_SRL = 0x02 | EXT_SPECIAL,
OPC_SRA = 0x03 | EXT_SPECIAL,
OPC_SLLV = 0x04 | EXT_SPECIAL,
OPC_SRLV = 0x06 | EXT_SPECIAL,
OPC_SRAV = 0x07 | EXT_SPECIAL,
/* Multiplication / division */
OPC_MULT = 0x18 | EXT_SPECIAL,
OPC_MULTU = 0x19 | EXT_SPECIAL,
OPC_DIV = 0x1A | EXT_SPECIAL,
OPC_DIVU = 0x1B | EXT_SPECIAL,
/* 2 registers arithmetic / logic */
OPC_ADD = 0x20 | EXT_SPECIAL,
OPC_ADDU = 0x21 | EXT_SPECIAL,
OPC_SUB = 0x22 | EXT_SPECIAL,
OPC_SUBU = 0x23 | EXT_SPECIAL,
OPC_AND = 0x24 | EXT_SPECIAL,
OPC_OR = 0x25 | EXT_SPECIAL,
OPC_XOR = 0x26 | EXT_SPECIAL,
OPC_NOR = 0x27 | EXT_SPECIAL,
OPC_SLT = 0x2A | EXT_SPECIAL,
OPC_SLTU = 0x2B | EXT_SPECIAL,
/* Jumps */
OPC_JR = 0x08 | EXT_SPECIAL,
OPC_JALR = 0x09 | EXT_SPECIAL,
/* Traps */
OPC_TGE = 0x30 | EXT_SPECIAL,
OPC_TGEU = 0x31 | EXT_SPECIAL,
OPC_TLT = 0x32 | EXT_SPECIAL,
OPC_TLTU = 0x33 | EXT_SPECIAL,
OPC_TEQ = 0x34 | EXT_SPECIAL,
OPC_TNE = 0x36 | EXT_SPECIAL,
/* HI / LO registers load & stores */
OPC_MFHI = 0x10 | EXT_SPECIAL,
OPC_MTHI = 0x11 | EXT_SPECIAL,
OPC_MFLO = 0x12 | EXT_SPECIAL,
OPC_MTLO = 0x13 | EXT_SPECIAL,
/* Conditional moves */
OPC_MOVZ = 0x0A | EXT_SPECIAL,
OPC_MOVN = 0x0B | EXT_SPECIAL,
OPC_MOVCI = 0x01 | EXT_SPECIAL,
/* Special */
OPC_PMON = 0x05 | EXT_SPECIAL,
OPC_SYSCALL = 0x0C | EXT_SPECIAL,
OPC_BREAK = 0x0D | EXT_SPECIAL,
OPC_SYNC = 0x0F | EXT_SPECIAL,
};
enum {
/* Mutiply & xxx operations */
OPC_MADD = 0x00 | EXT_SPECIAL2,
OPC_MADDU = 0x01 | EXT_SPECIAL2,
OPC_MUL = 0x02 | EXT_SPECIAL2,
OPC_MSUB = 0x04 | EXT_SPECIAL2,
OPC_MSUBU = 0x05 | EXT_SPECIAL2,
/* Misc */
OPC_CLZ = 0x20 | EXT_SPECIAL2,
OPC_CLO = 0x21 | EXT_SPECIAL2,
/* Special */
OPC_SDBBP = 0x3F | EXT_SPECIAL2,
};
/* Branch REGIMM */
enum {
OPC_BLTZ = 0x00 | EXT_REGIMM,
OPC_BLTZL = 0x02 | EXT_REGIMM,
OPC_BGEZ = 0x01 | EXT_REGIMM,
OPC_BGEZL = 0x03 | EXT_REGIMM,
OPC_BLTZAL = 0x10 | EXT_REGIMM,
OPC_BLTZALL = 0x12 | EXT_REGIMM,
OPC_BGEZAL = 0x11 | EXT_REGIMM,
OPC_BGEZALL = 0x13 | EXT_REGIMM,
OPC_TGEI = 0x08 | EXT_REGIMM,
OPC_TGEIU = 0x09 | EXT_REGIMM,
OPC_TLTI = 0x0A | EXT_REGIMM,
OPC_TLTIU = 0x0B | EXT_REGIMM,
OPC_TEQI = 0x0C | EXT_REGIMM,
OPC_TNEI = 0x0E | EXT_REGIMM,
};
enum {
/* Coprocessor 0 (MMU) */
OPC_MFC0 = 0x00 | EXT_CP0,
OPC_MTC0 = 0x04 | EXT_CP0,
OPC_TLBR = 0x01 | EXT_CP0,
OPC_TLBWI = 0x02 | EXT_CP0,
OPC_TLBWR = 0x06 | EXT_CP0,
OPC_TLBP = 0x08 | EXT_CP0,
OPC_ERET = 0x18 | EXT_CP0,
OPC_DERET = 0x1F | EXT_CP0,
OPC_WAIT = 0x20 | EXT_CP0,
};
int cpu_mips_exec(CPUMIPSState *s);
CPUMIPSState *cpu_mips_init(void);
uint32_t cpu_mips_get_clock (void);

12
target-mips/exec.h
View File

@ -19,27 +19,15 @@ typedef uint32_t host_uint_t;
register host_uint_t T0 asm(AREG1);
register host_uint_t T1 asm(AREG2);
register host_uint_t T2 asm(AREG3);
register host_int_t Ts0 asm(AREG1);
register host_int_t Ts1 asm(AREG2);
register host_int_t Ts2 asm(AREG3);
#define PARAM(n) ((uint32_t)PARAM##n)
#define SPARAM(n) ((int32_t)PARAM##n)
#if defined (USE_HOST_FLOAT_REGS)
register double FT0 asm(FREG0);
register double FT1 asm(FREG1);
register double FT2 asm(FREG2);
register float FTS0 asm(FREG0);
register float FTS1 asm(FREG1);
register float FTS2 asm(FREG2);
#else
#define FT0 (env->ft0.d)
#define FT1 (env->ft1.d)
#define FT2 (env->ft2.d)
#define FTS0 (env->ft0.f)
#define FTS1 (env->ft1.f)
#define FTS2 (env->ft2.f)
#endif
#if defined (DEBUG_OP)

58
target-mips/helper.c
View File

@ -17,7 +17,16 @@
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "exec.h"
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>
#include "cpu.h"
#include "exec-all.h"
/* MIPS32 4K MMU emulation */
#ifdef MIPS_USES_R4K_TLB
@ -142,57 +151,10 @@ target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
return -1;
return phys_addr;
}
#endif
#if !defined(CONFIG_USER_ONLY)
#define MMUSUFFIX _mmu
#define GETPC() (__builtin_return_address(0))
#define SHIFT 0
#include "softmmu_template.h"
#define SHIFT 1
#include "softmmu_template.h"
#define SHIFT 2
#include "softmmu_template.h"
#define SHIFT 3
#include "softmmu_template.h"
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
{
TranslationBlock *tb;
CPUState *saved_env;
unsigned long pc;
int ret;
/* XXX: hack to restore env in all cases, even if not called from
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */
pc = (unsigned long)retaddr;
tb = tb_find_pc(pc);
if (tb) {
/* the PC is inside the translated code. It means that we have
a virtual CPU fault */
cpu_restore_state(tb, env, pc, NULL);
}
}
do_raise_exception_err(env->exception_index, env->error_code);
}
env = saved_env;
}
void cpu_mips_init_mmu (CPUState *env)
{
}
#endif /* !defined(CONFIG_USER_ONLY) */
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

59
target-mips/op_helper.c
View File

@ -29,7 +29,6 @@ void cpu_loop_exit(void)
longjmp(env->jmp_env, 1);
}
__attribute__ (( regparm(2) ))
void do_raise_exception_err (uint32_t exception, int error_code)
{
#if 1
@ -42,7 +41,6 @@ void do_raise_exception_err (uint32_t exception, int error_code)
cpu_loop_exit();
}
__attribute__ (( regparm(1) ))
void do_raise_exception (uint32_t exception)
{
do_raise_exception_err(exception, 0);
@ -117,7 +115,6 @@ void do_msubu (void)
#endif
/* CP0 helpers */
__attribute__ (( regparm(2) ))
void do_mfc0 (int reg, int sel)
{
const unsigned char *rn;
@ -267,12 +264,10 @@ void do_mfc0 (int reg, int sel)
return;
}
__attribute__ (( regparm(2) ))
void do_mtc0 (int reg, int sel)
{
const unsigned char *rn;
uint32_t val, old, mask;
int i, raise;
if (sel != 0 && reg != 16 && reg != 28) {
val = -1;
@ -379,12 +374,15 @@ void do_mtc0 (int reg, int sel)
old = env->CP0_Cause;
env->CP0_Cause = val;
#if 0
{
int i;
/* Check if we ever asserted a software IRQ */
for (i = 0; i < 2; i++) {
mask = 0x100 << i;
if ((val & mask) & !(old & mask))
mips_set_irq(i);
}
}
#endif
rn = "Cause";
break;
@ -486,7 +484,6 @@ void do_mtc0 (int reg, int sel)
/* TLB management */
#if defined(MIPS_USES_R4K_TLB)
__attribute__ (( regparm(1) ))
static void invalidate_tb (int idx)
{
tlb_t *tlb;
@ -505,7 +502,6 @@ static void invalidate_tb (int idx)
}
}
__attribute__ (( regparm(1) ))
static void fill_tb (int idx)
{
tlb_t *tlb;
@ -584,7 +580,6 @@ void do_tlbr (void)
}
#endif
__attribute__ (( regparm(1) ))
void op_dump_ldst (const unsigned char *func)
{
if (loglevel)
@ -608,7 +603,6 @@ void debug_eret (void)
}
}
__attribute__ (( regparm(1) ))
void do_pmon (int function)
{
function /= 2;
@ -634,3 +628,50 @@ void do_pmon (int function)
break;
}
}
#if !defined(CONFIG_USER_ONLY)
#define MMUSUFFIX _mmu
#define GETPC() (__builtin_return_address(0))
#define SHIFT 0
#include "softmmu_template.h"
#define SHIFT 1
#include "softmmu_template.h"
#define SHIFT 2
#include "softmmu_template.h"
#define SHIFT 3
#include "softmmu_template.h"
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
{
TranslationBlock *tb;
CPUState *saved_env;
unsigned long pc;
int ret;
/* XXX: hack to restore env in all cases, even if not called from
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */
pc = (unsigned long)retaddr;
tb = tb_find_pc(pc);
if (tb) {
/* the PC is inside the translated code. It means that we have
a virtual CPU fault */
cpu_restore_state(tb, env, pc, NULL);
}
}
do_raise_exception_err(env->exception_index, env->error_code);
}
env = saved_env;
}
#endif

168
target-mips/translate.c
View File

@ -43,6 +43,174 @@ static uint32_t *gen_opparam_ptr;
#include "gen-op.h"
/* MIPS opcodes */
#define EXT_SPECIAL 0x100
#define EXT_SPECIAL2 0x200
#define EXT_REGIMM 0x300
#define EXT_CP0 0x400
#define EXT_CP1 0x500
#define EXT_CP2 0x600
#define EXT_CP3 0x700
enum {
/* indirect opcode tables */
OPC_SPECIAL = 0x00,
OPC_BREGIMM = 0x01,
OPC_CP0 = 0x10,
OPC_CP1 = 0x11,
OPC_CP2 = 0x12,
OPC_CP3 = 0x13,
OPC_SPECIAL2 = 0x1C,
/* arithmetic with immediate */
OPC_ADDI = 0x08,
OPC_ADDIU = 0x09,
OPC_SLTI = 0x0A,
OPC_SLTIU = 0x0B,
OPC_ANDI = 0x0C,
OPC_ORI = 0x0D,
OPC_XORI = 0x0E,
OPC_LUI = 0x0F,
/* Jump and branches */
OPC_J = 0x02,
OPC_JAL = 0x03,
OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */
OPC_BEQL = 0x14,
OPC_BNE = 0x05,
OPC_BNEL = 0x15,
OPC_BLEZ = 0x06,
OPC_BLEZL = 0x16,
OPC_BGTZ = 0x07,
OPC_BGTZL = 0x17,
OPC_JALX = 0x1D, /* MIPS 16 only */
/* Load and stores */
OPC_LB = 0x20,
OPC_LH = 0x21,
OPC_LWL = 0x22,
OPC_LW = 0x23,
OPC_LBU = 0x24,
OPC_LHU = 0x25,
OPC_LWR = 0x26,
OPC_SB = 0x28,
OPC_SH = 0x29,
OPC_SWL = 0x2A,
OPC_SW = 0x2B,
OPC_SWR = 0x2E,
OPC_LL = 0x30,
OPC_SC = 0x38,
/* Floating point load/store */
OPC_LWC1 = 0x31,
OPC_LWC2 = 0x32,
OPC_LDC1 = 0x35,
OPC_LDC2 = 0x36,
OPC_SWC1 = 0x39,
OPC_SWC2 = 0x3A,
OPC_SDC1 = 0x3D,
OPC_SDC2 = 0x3E,
/* Cache and prefetch */
OPC_CACHE = 0x2F,
OPC_PREF = 0x33,
};
/* MIPS special opcodes */
enum {
/* Shifts */
OPC_SLL = 0x00 | EXT_SPECIAL,
/* NOP is SLL r0, r0, 0 */
/* SSNOP is SLL r0, r0, 1 */
OPC_SRL = 0x02 | EXT_SPECIAL,
OPC_SRA = 0x03 | EXT_SPECIAL,
OPC_SLLV = 0x04 | EXT_SPECIAL,
OPC_SRLV = 0x06 | EXT_SPECIAL,
OPC_SRAV = 0x07 | EXT_SPECIAL,
/* Multiplication / division */
OPC_MULT = 0x18 | EXT_SPECIAL,
OPC_MULTU = 0x19 | EXT_SPECIAL,
OPC_DIV = 0x1A | EXT_SPECIAL,
OPC_DIVU = 0x1B | EXT_SPECIAL,
/* 2 registers arithmetic / logic */
OPC_ADD = 0x20 | EXT_SPECIAL,
OPC_ADDU = 0x21 | EXT_SPECIAL,
OPC_SUB = 0x22 | EXT_SPECIAL,
OPC_SUBU = 0x23 | EXT_SPECIAL,
OPC_AND = 0x24 | EXT_SPECIAL,
OPC_OR = 0x25 | EXT_SPECIAL,
OPC_XOR = 0x26 | EXT_SPECIAL,
OPC_NOR = 0x27 | EXT_SPECIAL,
OPC_SLT = 0x2A | EXT_SPECIAL,
OPC_SLTU = 0x2B | EXT_SPECIAL,
/* Jumps */
OPC_JR = 0x08 | EXT_SPECIAL,
OPC_JALR = 0x09 | EXT_SPECIAL,
/* Traps */
OPC_TGE = 0x30 | EXT_SPECIAL,
OPC_TGEU = 0x31 | EXT_SPECIAL,
OPC_TLT = 0x32 | EXT_SPECIAL,
OPC_TLTU = 0x33 | EXT_SPECIAL,
OPC_TEQ = 0x34 | EXT_SPECIAL,
OPC_TNE = 0x36 | EXT_SPECIAL,
/* HI / LO registers load & stores */
OPC_MFHI = 0x10 | EXT_SPECIAL,
OPC_MTHI = 0x11 | EXT_SPECIAL,
OPC_MFLO = 0x12 | EXT_SPECIAL,
OPC_MTLO = 0x13 | EXT_SPECIAL,
/* Conditional moves */
OPC_MOVZ = 0x0A | EXT_SPECIAL,
OPC_MOVN = 0x0B | EXT_SPECIAL,
OPC_MOVCI = 0x01 | EXT_SPECIAL,
/* Special */
OPC_PMON = 0x05 | EXT_SPECIAL,
OPC_SYSCALL = 0x0C | EXT_SPECIAL,
OPC_BREAK = 0x0D | EXT_SPECIAL,
OPC_SYNC = 0x0F | EXT_SPECIAL,
};
enum {
/* Mutiply & xxx operations */
OPC_MADD = 0x00 | EXT_SPECIAL2,
OPC_MADDU = 0x01 | EXT_SPECIAL2,
OPC_MUL = 0x02 | EXT_SPECIAL2,
OPC_MSUB = 0x04 | EXT_SPECIAL2,
OPC_MSUBU = 0x05 | EXT_SPECIAL2,
/* Misc */
OPC_CLZ = 0x20 | EXT_SPECIAL2,
OPC_CLO = 0x21 | EXT_SPECIAL2,
/* Special */
OPC_SDBBP = 0x3F | EXT_SPECIAL2,
};
/* Branch REGIMM */
enum {
OPC_BLTZ = 0x00 | EXT_REGIMM,
OPC_BLTZL = 0x02 | EXT_REGIMM,
OPC_BGEZ = 0x01 | EXT_REGIMM,
OPC_BGEZL = 0x03 | EXT_REGIMM,
OPC_BLTZAL = 0x10 | EXT_REGIMM,
OPC_BLTZALL = 0x12 | EXT_REGIMM,
OPC_BGEZAL = 0x11 | EXT_REGIMM,
OPC_BGEZALL = 0x13 | EXT_REGIMM,
OPC_TGEI = 0x08 | EXT_REGIMM,
OPC_TGEIU = 0x09 | EXT_REGIMM,
OPC_TLTI = 0x0A | EXT_REGIMM,
OPC_TLTIU = 0x0B | EXT_REGIMM,
OPC_TEQI = 0x0C | EXT_REGIMM,
OPC_TNEI = 0x0E | EXT_REGIMM,
};
enum {
/* Coprocessor 0 (MMU) */
OPC_MFC0 = 0x00 | EXT_CP0,
OPC_MTC0 = 0x04 | EXT_CP0,
OPC_TLBR = 0x01 | EXT_CP0,
OPC_TLBWI = 0x02 | EXT_CP0,
OPC_TLBWR = 0x06 | EXT_CP0,
OPC_TLBP = 0x08 | EXT_CP0,
OPC_ERET = 0x18 | EXT_CP0,
OPC_DERET = 0x1F | EXT_CP0,
OPC_WAIT = 0x20 | EXT_CP0,
};
const unsigned char *regnames[] =
{ "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",