hw/block/nvme: support for multi-controller in subsystem

We have nvme-subsys and nvme devices mapped together.  To support
multi-controller scheme to this setup, controller identifier(id) has to
be managed.  Earlier, cntlid(controller id) used to be always 0 because
we didn't have any subsystem scheme that controller id matters.

This patch introduced 'cntlid' attribute to the nvme controller
instance(NvmeCtrl) and make it allocated by the nvme-subsys device
mapped to the controller.  If nvme-subsys is not given to the
controller, then it will always be 0 as it was.

Added 'ctrls' array in the nvme-subsys instance to manage attached
controllers to the subsystem with a limit(32).  This patch didn't take
list for the controllers to make it seamless with nvme-ns device.

Signed-off-by: Minwoo Im <minwoo.im.dev@gmail.com>
Tested-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
This commit is contained in:
Minwoo Im 2021-01-24 11:54:48 +09:00 committed by Klaus Jensen
parent 66b7e9bed0
commit e36a261d4b
4 changed files with 55 additions and 0 deletions

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@ -22,6 +22,27 @@
#include "nvme.h" #include "nvme.h"
#include "nvme-subsys.h" #include "nvme-subsys.h"
int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp)
{
NvmeSubsystem *subsys = n->subsys;
int cntlid;
for (cntlid = 0; cntlid < ARRAY_SIZE(subsys->ctrls); cntlid++) {
if (!subsys->ctrls[cntlid]) {
break;
}
}
if (cntlid == ARRAY_SIZE(subsys->ctrls)) {
error_setg(errp, "no more free controller id");
return -1;
}
subsys->ctrls[cntlid] = n;
return cntlid;
}
static void nvme_subsys_setup(NvmeSubsystem *subsys) static void nvme_subsys_setup(NvmeSubsystem *subsys)
{ {
const char *nqn = subsys->params.nqn ? const char *nqn = subsys->params.nqn ?

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@ -21,9 +21,13 @@ typedef struct NvmeSubsystem {
DeviceState parent_obj; DeviceState parent_obj;
uint8_t subnqn[256]; uint8_t subnqn[256];
NvmeCtrl *ctrls[NVME_SUBSYS_MAX_CTRLS];
struct { struct {
char *nqn; char *nqn;
} params; } params;
} NvmeSubsystem; } NvmeSubsystem;
int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp);
#endif /* NVME_SUBSYS_H */ #endif /* NVME_SUBSYS_H */

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@ -4448,6 +4448,9 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' '); strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' ');
strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' '); strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' ');
id->cntlid = cpu_to_le16(n->cntlid);
id->rab = 6; id->rab = 6;
id->ieee[0] = 0x00; id->ieee[0] = 0x00;
id->ieee[1] = 0x02; id->ieee[1] = 0x02;
@ -4494,6 +4497,10 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
id->psd[0].enlat = cpu_to_le32(0x10); id->psd[0].enlat = cpu_to_le32(0x10);
id->psd[0].exlat = cpu_to_le32(0x4); id->psd[0].exlat = cpu_to_le32(0x4);
if (n->subsys) {
id->cmic |= NVME_CMIC_MULTI_CTRL;
}
NVME_CAP_SET_MQES(n->bar.cap, 0x7ff); NVME_CAP_SET_MQES(n->bar.cap, 0x7ff);
NVME_CAP_SET_CQR(n->bar.cap, 1); NVME_CAP_SET_CQR(n->bar.cap, 1);
NVME_CAP_SET_TO(n->bar.cap, 0xf); NVME_CAP_SET_TO(n->bar.cap, 0xf);
@ -4508,6 +4515,24 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
n->bar.intmc = n->bar.intms = 0; n->bar.intmc = n->bar.intms = 0;
} }
static int nvme_init_subsys(NvmeCtrl *n, Error **errp)
{
int cntlid;
if (!n->subsys) {
return 0;
}
cntlid = nvme_subsys_register_ctrl(n, errp);
if (cntlid < 0) {
return -1;
}
n->cntlid = cntlid;
return 0;
}
static void nvme_realize(PCIDevice *pci_dev, Error **errp) static void nvme_realize(PCIDevice *pci_dev, Error **errp)
{ {
NvmeCtrl *n = NVME(pci_dev); NvmeCtrl *n = NVME(pci_dev);
@ -4528,6 +4553,10 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
return; return;
} }
if (nvme_init_subsys(n, errp)) {
error_propagate(errp, local_err);
return;
}
nvme_init_ctrl(n, pci_dev); nvme_init_ctrl(n, pci_dev);
/* setup a namespace if the controller drive property was given */ /* setup a namespace if the controller drive property was given */

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@ -134,6 +134,7 @@ typedef struct NvmeCtrl {
NvmeBus bus; NvmeBus bus;
BlockConf conf; BlockConf conf;
uint16_t cntlid;
bool qs_created; bool qs_created;
uint32_t page_size; uint32_t page_size;
uint16_t page_bits; uint16_t page_bits;