hw/block/nvme: support for multi-controller in subsystem
We have nvme-subsys and nvme devices mapped together. To support multi-controller scheme to this setup, controller identifier(id) has to be managed. Earlier, cntlid(controller id) used to be always 0 because we didn't have any subsystem scheme that controller id matters. This patch introduced 'cntlid' attribute to the nvme controller instance(NvmeCtrl) and make it allocated by the nvme-subsys device mapped to the controller. If nvme-subsys is not given to the controller, then it will always be 0 as it was. Added 'ctrls' array in the nvme-subsys instance to manage attached controllers to the subsystem with a limit(32). This patch didn't take list for the controllers to make it seamless with nvme-ns device. Signed-off-by: Minwoo Im <minwoo.im.dev@gmail.com> Tested-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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@ -22,6 +22,27 @@
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#include "nvme.h"
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#include "nvme-subsys.h"
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int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp)
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{
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NvmeSubsystem *subsys = n->subsys;
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int cntlid;
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for (cntlid = 0; cntlid < ARRAY_SIZE(subsys->ctrls); cntlid++) {
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if (!subsys->ctrls[cntlid]) {
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break;
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}
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}
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if (cntlid == ARRAY_SIZE(subsys->ctrls)) {
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error_setg(errp, "no more free controller id");
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return -1;
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}
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subsys->ctrls[cntlid] = n;
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return cntlid;
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}
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static void nvme_subsys_setup(NvmeSubsystem *subsys)
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{
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const char *nqn = subsys->params.nqn ?
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@ -21,9 +21,13 @@ typedef struct NvmeSubsystem {
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DeviceState parent_obj;
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uint8_t subnqn[256];
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NvmeCtrl *ctrls[NVME_SUBSYS_MAX_CTRLS];
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struct {
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char *nqn;
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} params;
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} NvmeSubsystem;
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int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp);
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#endif /* NVME_SUBSYS_H */
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@ -4448,6 +4448,9 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
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strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
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strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' ');
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strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' ');
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id->cntlid = cpu_to_le16(n->cntlid);
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id->rab = 6;
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id->ieee[0] = 0x00;
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id->ieee[1] = 0x02;
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@ -4494,6 +4497,10 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
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id->psd[0].enlat = cpu_to_le32(0x10);
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id->psd[0].exlat = cpu_to_le32(0x4);
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if (n->subsys) {
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id->cmic |= NVME_CMIC_MULTI_CTRL;
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}
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NVME_CAP_SET_MQES(n->bar.cap, 0x7ff);
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NVME_CAP_SET_CQR(n->bar.cap, 1);
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NVME_CAP_SET_TO(n->bar.cap, 0xf);
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@ -4508,6 +4515,24 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
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n->bar.intmc = n->bar.intms = 0;
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}
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static int nvme_init_subsys(NvmeCtrl *n, Error **errp)
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{
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int cntlid;
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if (!n->subsys) {
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return 0;
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}
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cntlid = nvme_subsys_register_ctrl(n, errp);
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if (cntlid < 0) {
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return -1;
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}
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n->cntlid = cntlid;
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return 0;
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}
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static void nvme_realize(PCIDevice *pci_dev, Error **errp)
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{
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NvmeCtrl *n = NVME(pci_dev);
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@ -4528,6 +4553,10 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
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return;
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}
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if (nvme_init_subsys(n, errp)) {
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error_propagate(errp, local_err);
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return;
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}
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nvme_init_ctrl(n, pci_dev);
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/* setup a namespace if the controller drive property was given */
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@ -134,6 +134,7 @@ typedef struct NvmeCtrl {
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NvmeBus bus;
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BlockConf conf;
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uint16_t cntlid;
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bool qs_created;
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uint32_t page_size;
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uint16_t page_bits;
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