Sparc32: convert Sun4c interrupt controller to qdev
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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7fc067350c
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@ -21,9 +21,12 @@
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sun4m.h"
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#include "monitor.h"
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#include "sysbus.h"
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//#define DEBUG_IRQ_COUNT
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//#define DEBUG_IRQ
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@ -42,10 +45,11 @@
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#define MAX_PILS 16
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typedef struct Sun4c_INTCTLState {
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SysBusDevice busdev;
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#ifdef DEBUG_IRQ_COUNT
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uint64_t irq_count;
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#endif
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qemu_irq *cpu_irqs;
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qemu_irq cpu_irqs[MAX_PILS];
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const uint32_t *intbit_to_level;
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uint32_t pil_out;
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uint8_t reg;
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@ -194,25 +198,54 @@ static void sun4c_intctl_reset(void *opaque)
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s->pending = 0;
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}
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void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
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qemu_irq *parent_irq)
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DeviceState *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq *parent_irq)
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{
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int sun4c_intctl_io_memory;
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Sun4c_INTCTLState *s;
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DeviceState *dev;
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SysBusDevice *s;
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unsigned int i;
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s = qemu_mallocz(sizeof(Sun4c_INTCTLState));
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dev = qdev_create(NULL, "sun4c_intctl");
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qdev_init(dev);
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sun4c_intctl_io_memory = cpu_register_io_memory(sun4c_intctl_mem_read,
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sun4c_intctl_mem_write, s);
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cpu_register_physical_memory(addr, INTCTL_SIZE, sun4c_intctl_io_memory);
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s->cpu_irqs = parent_irq;
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s = sysbus_from_qdev(dev);
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register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save,
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sun4c_intctl_load, s);
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for (i = 0; i < MAX_PILS; i++) {
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sysbus_connect_irq(s, i, parent_irq[i]);
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}
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sysbus_mmio_map(s, 0, addr);
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qemu_register_reset(sun4c_intctl_reset, s);
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*irq = qemu_allocate_irqs(sun4c_set_irq, s, 8);
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sun4c_intctl_reset(s);
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return s;
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return dev;
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}
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static void sun4c_intctl_init1(SysBusDevice *dev)
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{
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Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);
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int io_memory;
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unsigned int i;
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io_memory = cpu_register_io_memory(sun4c_intctl_mem_read,
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sun4c_intctl_mem_write, s);
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sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
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qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
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for (i = 0; i < MAX_PILS; i++) {
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sysbus_init_irq(dev, &s->cpu_irqs[i]);
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}
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register_savevm("sun4c_intctl", -1, 1, sun4c_intctl_save,
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sun4c_intctl_load, s);
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qemu_register_reset(sun4c_intctl_reset, s);
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sun4c_intctl_reset(s);
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}
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static SysBusDeviceInfo sun4c_intctl_info = {
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.init = sun4c_intctl_init1,
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.qdev.name = "sun4c_intctl",
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.qdev.size = sizeof(Sun4c_INTCTLState),
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};
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static void sun4c_intctl_register_devices(void)
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{
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sysbus_register_withprop(&sun4c_intctl_info);
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}
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device_init(sun4c_intctl_register_devices)
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11
hw/sun4m.c
11
hw/sun4m.c
@ -1502,13 +1502,15 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
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{
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CPUState *env;
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void *iommu, *espdma, *ledma, *nvram;
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qemu_irq *cpu_irqs, *slavio_irq, espdma_irq, ledma_irq;
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qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
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qemu_irq *esp_reset, *le_reset;
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qemu_irq fdc_tc;
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unsigned long kernel_size;
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BlockDriverState *fd[MAX_FD];
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int drive_index;
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void *fw_cfg;
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DeviceState *dev;
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unsigned int i;
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/* init CPU */
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if (!cpu_model)
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@ -1521,8 +1523,11 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
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prom_init(hwdef->slavio_base, bios_name);
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slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
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&slavio_irq, cpu_irqs);
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dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
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for (i = 0; i < 8; i++) {
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slavio_irq[i] = qdev_get_gpio_in(dev, i);
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}
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iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
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slavio_irq[hwdef->me_irq]);
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@ -39,8 +39,7 @@ void slavio_irq_info(Monitor *mon, void *opaque);
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DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq);
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/* sun4c_intctl.c */
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void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
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qemu_irq *parent_irq);
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DeviceState *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq *parent_irq);
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void sun4c_pic_info(Monitor *mon, void *opaque);
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void sun4c_irq_info(Monitor *mon, void *opaque);
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