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tcg/loongarch64: Simplify constraints on qemu_ld/st

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The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers.  Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-04-03 17:36:02 +00:00
parent eb491329f6
commit e3205306d8
3 changed files with 4 additions and 22 deletions
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2
tcg/loongarch64/tcg-target-con-set.h
View File

@ -17,9 +17,7 @@
C_O0_I1(r) C_O0_I1(r)
C_O0_I2(rZ, r) C_O0_I2(rZ, r)
C_O0_I2(rZ, rZ) C_O0_I2(rZ, rZ)
C_O0_I2(LZ, L)
C_O1_I1(r, r) C_O1_I1(r, r)
C_O1_I1(r, L)
C_O1_I2(r, r, rC) C_O1_I2(r, r, rC)
C_O1_I2(r, r, ri) C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI) C_O1_I2(r, r, rI)

1
tcg/loongarch64/tcg-target-con-str.h
View File

@ -14,7 +14,6 @@
* REGS(letter, register_mask) * REGS(letter, register_mask)
*/ */
REGS('r', ALL_GENERAL_REGS) REGS('r', ALL_GENERAL_REGS)
REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
/* /*
* Define constraint letters for constants: * Define constraint letters for constants:

23
tcg/loongarch64/tcg-target.c.inc
View File

@ -133,18 +133,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define TCG_CT_CONST_C12 0x1000 #define TCG_CT_CONST_C12 0x1000
#define TCG_CT_CONST_WSZ 0x2000 #define TCG_CT_CONST_WSZ 0x2000
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
/*
* For softmmu, we need to avoid conflicts with the first 5
* argument registers to call the helper. Some of these are
* also used for the tlb lookup.
*/
#ifdef CONFIG_SOFTMMU
#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5)
#else
#define SOFTMMU_RESERVE_REGS 0
#endif
static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
{ {
@ -1541,16 +1530,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_st32_i64: case INDEX_op_st32_i64:
case INDEX_op_st_i32: case INDEX_op_st_i32:
case INDEX_op_st_i64: case INDEX_op_st_i64:
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
return C_O0_I2(rZ, r); return C_O0_I2(rZ, r);
case INDEX_op_brcond_i32: case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64: case INDEX_op_brcond_i64:
return C_O0_I2(rZ, rZ); return C_O0_I2(rZ, rZ);
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
return C_O0_I2(LZ, L);
case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i32:
case INDEX_op_ext8s_i64: case INDEX_op_ext8s_i64:
case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i32:
@ -1586,11 +1573,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld32u_i64: case INDEX_op_ld32u_i64:
case INDEX_op_ld_i32: case INDEX_op_ld_i32:
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
return C_O1_I1(r, r);
case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_ld_i64:
return C_O1_I1(r, L); return C_O1_I1(r, r);
case INDEX_op_andc_i32: case INDEX_op_andc_i32:
case INDEX_op_andc_i64: case INDEX_op_andc_i64: