target/arm: Simplify DC_ZVA
Now that we know that the operation is on a single page, we need not loop over pages while probing. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1119,85 +1119,41 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
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* (which matches the usual QEMU behaviour of not implementing either
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* alignment faults or any memory attribute handling).
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*/
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ARMCPU *cpu = env_archcpu(env);
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uint64_t blocklen = 4 << cpu->dcz_blocksize;
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int blocklen = 4 << env_archcpu(env)->dcz_blocksize;
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uint64_t vaddr = vaddr_in & ~(blocklen - 1);
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int mmu_idx = cpu_mmu_index(env, false);
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void *mem;
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/*
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* Trapless lookup. In addition to actual invalid page, may
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* return NULL for I/O, watchpoints, clean pages, etc.
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*/
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mem = tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx);
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#ifndef CONFIG_USER_ONLY
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{
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if (unlikely(!mem)) {
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uintptr_t ra = GETPC();
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/*
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* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
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* the block size so we might have to do more than one TLB lookup.
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* We know that in fact for any v8 CPU the page size is at least 4K
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* and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
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* 1K as an artefact of legacy v5 subpage support being present in the
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* same QEMU executable. So in practice the hostaddr[] array has
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* two entries, given the current setting of TARGET_PAGE_BITS_MIN.
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* Trap if accessing an invalid page. DC_ZVA requires that we supply
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* the original pointer for an invalid page. But watchpoints require
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* that we probe the actual space. So do both.
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*/
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int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
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void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)];
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int try, i;
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unsigned mmu_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
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(void) probe_write(env, vaddr_in, 1, mmu_idx, ra);
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mem = probe_write(env, vaddr, blocklen, mmu_idx, ra);
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assert(maxidx <= ARRAY_SIZE(hostaddr));
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for (try = 0; try < 2; try++) {
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for (i = 0; i < maxidx; i++) {
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hostaddr[i] = tlb_vaddr_to_host(env,
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vaddr + TARGET_PAGE_SIZE * i,
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1, mmu_idx);
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if (!hostaddr[i]) {
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break;
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}
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}
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if (i == maxidx) {
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/*
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* If it's all in the TLB it's fair game for just writing to;
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* we know we don't need to update dirty status, etc.
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*/
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for (i = 0; i < maxidx - 1; i++) {
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memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
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}
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memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
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return;
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}
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if (unlikely(!mem)) {
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/*
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* OK, try a store and see if we can populate the tlb. This
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* might cause an exception if the memory isn't writable,
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* in which case we will longjmp out of here. We must for
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* this purpose use the actual register value passed to us
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* so that we get the fault address right.
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* The only remaining reason for mem == NULL is I/O.
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* Just do a series of byte writes as the architecture demands.
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*/
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helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC());
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/* Now we can populate the other TLB entries, if any */
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for (i = 0; i < maxidx; i++) {
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uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
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if (va != (vaddr_in & TARGET_PAGE_MASK)) {
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helper_ret_stb_mmu(env, va, 0, oi, GETPC());
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}
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for (int i = 0; i < blocklen; i++) {
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cpu_stb_mmuidx_ra(env, vaddr + i, 0, mmu_idx, ra);
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}
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}
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/*
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* Slow path (probably attempt to do this to an I/O device or
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* similar, or clearing of a block of code we have translations
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* cached for). Just do a series of byte writes as the architecture
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* demands. It's not worth trying to use a cpu_physical_memory_map(),
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* memset(), unmap() sequence here because:
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* + we'd need to account for the blocksize being larger than a page
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* + the direct-RAM access case is almost always going to be dealt
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* with in the fastpath code above, so there's no speed benefit
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* + we would have to deal with the map returning NULL because the
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* bounce buffer was in use
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*/
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for (i = 0; i < blocklen; i++) {
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helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC());
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return;
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}
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}
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#else
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memset(g2h(vaddr), 0, blocklen);
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#endif
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memset(mem, 0, blocklen);
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}
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