hw/timer/m48t59: Convert debug printf()s to trace events
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20200117165809.31067-3-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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@ -26,11 +26,6 @@
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#ifndef HW_M48T59_INTERNAL_H
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#define HW_M48T59_INTERNAL_H
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#define M48T59_DEBUG 0
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#define NVRAM_PRINTF(fmt, ...) do { \
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if (M48T59_DEBUG) { printf(fmt , ## __VA_ARGS__); } } while (0)
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/*
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* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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* alarm and a watchdog timer and related control registers. In the
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@ -35,6 +35,7 @@
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#include "exec/address-spaces.h"
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#include "qemu/bcd.h"
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#include "qemu/module.h"
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#include "trace.h"
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#include "m48t59-internal.h"
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#include "migration/vmstate.h"
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@ -192,8 +193,7 @@ void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
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struct tm tm;
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int tmp;
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if (addr > 0x1FF8 && addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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trace_m48txx_nvram_mem_write(addr, val);
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/* check for NVRAM access */
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if ((NVRAM->model == 2 && addr < 0x7f8) ||
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@ -450,8 +450,7 @@ uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
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}
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break;
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}
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if (addr > 0x1FF9 && addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
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trace_m48txx_nvram_mem_read(addr, retval);
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return retval;
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}
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@ -462,7 +461,7 @@ static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
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{
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M48t59State *NVRAM = opaque;
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NVRAM_PRINTF("%s: 0x%"HWADDR_PRIx" => 0x%"PRIx64"\n", __func__, addr, val);
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trace_m48txx_nvram_io_write(addr, val);
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switch (addr) {
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case 0:
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NVRAM->addr &= ~0x00FF;
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@ -494,7 +493,7 @@ static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
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retval = -1;
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break;
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}
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NVRAM_PRINTF("%s: 0x%"HWADDR_PRIx" <= 0x%08x\n", __func__, addr, retval);
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trace_m48txx_nvram_io_read(addr, retval);
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return retval;
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}
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@ -17,3 +17,9 @@ pl031_set_alarm(uint32_t ticks) "alarm set for %u ticks"
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# aspeed-rtc.c
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aspeed_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64
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aspeed_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64
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# m48t59.c
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m48txx_nvram_io_read(uint64_t addr, uint64_t value) "io read addr:0x%04" PRIx64 " value:0x%02" PRIx64
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m48txx_nvram_io_write(uint64_t addr, uint64_t value) "io write addr:0x%04" PRIx64 " value:0x%02" PRIx64
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m48txx_nvram_mem_read(uint32_t addr, uint32_t value) "mem read addr:0x%04x value:0x%02x"
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m48txx_nvram_mem_write(uint32_t addr, uint32_t value) "mem write addr:0x%04x value:0x%02x"
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