target/openrisc: Convert dec_logic
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -20,6 +20,7 @@
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&dab d a b
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&da d a
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&ab a b
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&dal d a l
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####
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# System Instructions
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@ -130,3 +131,8 @@ l_mac 110001 ----- a:5 b:5 ------- 0001
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l_macu 110001 ----- a:5 b:5 ------- 0011
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l_msb 110001 ----- a:5 b:5 ------- 0010
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l_msbu 110001 ----- a:5 b:5 ------- 0100
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l_slli 101110 d:5 a:5 -------- 00 l:6
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l_srli 101110 d:5 a:5 -------- 01 l:6
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l_srai 101110 d:5 a:5 -------- 10 l:6
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l_rori 101110 d:5 a:5 -------- 11 l:6
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@ -998,42 +998,36 @@ static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn)
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return true;
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}
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static void dec_logic(DisasContext *dc, uint32_t insn)
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static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn)
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{
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uint32_t op0;
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uint32_t rd, ra, L6, S6;
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op0 = extract32(insn, 6, 2);
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rd = extract32(insn, 21, 5);
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ra = extract32(insn, 16, 5);
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L6 = extract32(insn, 0, 6);
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S6 = L6 & (TARGET_LONG_BITS - 1);
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LOG_DIS("l.slli r%d, r%d, %d\n", a->d, a->a, a->l);
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check_r0_write(a->d);
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tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
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return true;
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}
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check_r0_write(rd);
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switch (op0) {
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case 0x00: /* l.slli */
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LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6);
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tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], S6);
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break;
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static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn)
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{
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LOG_DIS("l.srli r%d, r%d, %d\n", a->d, a->a, a->l);
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check_r0_write(a->d);
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tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
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return true;
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}
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case 0x01: /* l.srli */
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LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6);
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tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], S6);
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break;
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static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn)
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{
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LOG_DIS("l.srai r%d, r%d, %d\n", a->d, a->a, a->l);
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check_r0_write(a->d);
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tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
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return true;
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}
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case 0x02: /* l.srai */
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LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6);
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tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], S6);
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break;
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case 0x03: /* l.rori */
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LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6);
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tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], S6);
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break;
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default:
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gen_illegal_exception(dc);
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break;
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}
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static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn)
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{
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LOG_DIS("l.rori r%d, r%d, %d\n", a->d, a->a, a->l);
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check_r0_write(a->d);
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tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
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return true;
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}
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static void dec_M(DisasContext *dc, uint32_t insn)
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@ -1490,10 +1484,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
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dec_M(dc, insn);
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break;
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case 0x2e:
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dec_logic(dc, insn);
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break;
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case 0x2f:
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dec_compi(dc, insn);
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break;
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