mirror of https://gitlab.com/qemu-project/qemu
target-arm: A64: Add top level decode for SIMD 3-same group
Add top level decode for the A64 SIMD three regs same group (C3.6.16), splitting it into the pairwise, logical, float and integer subgroups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -5920,6 +5920,30 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
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}
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}
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}
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}
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/* Logic op (opcode == 3) subgroup of C3.6.16. */
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static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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}
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/* Pairwise op subgroup of C3.6.16. */
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static void disas_simd_3same_pair(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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}
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/* Floating point op subgroup of C3.6.16. */
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static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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}
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/* Integer op subgroup of C3.6.16. */
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static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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}
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/* C3.6.16 AdvSIMD three same
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/* C3.6.16 AdvSIMD three same
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* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
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* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
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* +---+---+---+-----------+------+---+------+--------+---+------+------+
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* +---+---+---+-----------+------+---+------+--------+---+------+------+
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@ -5928,7 +5952,26 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
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*/
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*/
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static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
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static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
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{
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{
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unsupported_encoding(s, insn);
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int opcode = extract32(insn, 11, 5);
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switch (opcode) {
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case 0x3: /* logic ops */
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disas_simd_3same_logic(s, insn);
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break;
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case 0x17: /* ADDP */
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case 0x14: /* SMAXP, UMAXP */
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case 0x15: /* SMINP, UMINP */
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/* Pairwise operations */
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disas_simd_3same_pair(s, insn);
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break;
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case 0x18 ... 0x31:
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/* floating point ops, sz[1] and U are part of opcode */
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disas_simd_3same_float(s, insn);
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break;
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default:
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disas_simd_3same_int(s, insn);
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break;
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}
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}
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}
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/* C3.6.17 AdvSIMD two reg misc
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/* C3.6.17 AdvSIMD two reg misc
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