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riscv: sifive_u: Generate hfclk and rtcclk nodes

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To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bin Meng 2019-09-06 09:20:09 -07:00 committed by Palmer Dabbelt
parent 0d95299468
commit e1724d09a6
No known key found for this signature in database
GPG Key ID: EF4CA1502CCBAB41
2 changed files with 25 additions and 0 deletions
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23
hw/riscv/sifive_u.c
View File

@ -79,6 +79,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
char ethclk_names[] = "pclk\0hclk\0tx_clk"; char ethclk_names[] = "pclk\0hclk\0tx_clk";
uint32_t plic_phandle, ethclk_phandle, phandle = 1; uint32_t plic_phandle, ethclk_phandle, phandle = 1;
uint32_t uartclk_phandle; uint32_t uartclk_phandle;
uint32_t hfclk_phandle, rtcclk_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size); fdt = s->fdt = create_device_tree(&s->fdt_size);
if (!fdt) { if (!fdt) {
@ -97,6 +98,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
hfclk_phandle = phandle++;
nodename = g_strdup_printf("/hfclk");
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
SIFIVE_U_HFCLK_FREQ);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
g_free(nodename);
rtcclk_phandle = phandle++;
nodename = g_strdup_printf("/rtcclk");
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
SIFIVE_U_RTCCLK_FREQ);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
g_free(nodename);
nodename = g_strdup_printf("/memory@%lx", nodename = g_strdup_printf("/memory@%lx",
(long)memmap[SIFIVE_U_DRAM].base); (long)memmap[SIFIVE_U_DRAM].base);
qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_add_subnode(fdt, nodename);

2
include/hw/riscv/sifive_u.h
View File

@ -69,6 +69,8 @@ enum {
enum { enum {
SIFIVE_U_CLOCK_FREQ = 1000000000, SIFIVE_U_CLOCK_FREQ = 1000000000,
SIFIVE_U_HFCLK_FREQ = 33333333,
SIFIVE_U_RTCCLK_FREQ = 1000000,
SIFIVE_U_GEM_CLOCK_FREQ = 125000000 SIFIVE_U_GEM_CLOCK_FREQ = 125000000
}; };