Merge branch 'tcg-ppc64' of git://github.com/rth7680/qemu
* 'tcg-ppc64' of git://github.com/rth7680/qemu: (33 commits) tcg-ppc64: Handle deposit of zero tcg-ppc64: Implement mulu2/muls2_i64 tcg-ppc64: Implement add2/sub2_i64 tcg-ppc64: Use getauxval for ISA detection tcg-ppc64: Implement movcond tcg-ppc64: Use ISEL for setcond tcg-ppc64: Use MFOCRF instead of MFCR tcg-ppc64: Cleanup i32 constants to tcg_out_cmp tcg-ppc64: Use TCGType throughout compares tcg-ppc64: Use I constraint for mul tcg-ppc64: Implement deposit tcg-ppc64: Handle constant inputs for some compound logicals tcg-ppc64: Implement compound logicals tcg-ppc64: Implement bswap64 tcg-ppc64: Implement bswap16 and bswap32 tcg-ppc64: Implement rotates tcg-ppc64: Streamline qemu_ld/st insn selection tcg-ppc64: Use automatic implementation of ext32u_i64 tcg-ppc64: Improve and_i64 with constant tcg-ppc64: Improve and_i32 with constant ...
This commit is contained in:
Aurelien Jarno
commit
e0e367bad7
18
configure
vendored
18
configure
vendored
@ -3308,6 +3308,20 @@ if compile_prog "" "" ; then
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int128=yes
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fi
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########################################
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# check if getauxval is available.
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getauxval=no
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cat > $TMPC << EOF
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#include <sys/auxv.h>
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int main(void) {
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return getauxval(AT_HWCAP) == 0;
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}
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EOF
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if compile_prog "" "" ; then
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getauxval=yes
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fi
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##########################################
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# End of CC checks
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# After here, no more $cc or $ld runs
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@ -3858,6 +3872,10 @@ if test "$int128" = "yes" ; then
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echo "CONFIG_INT128=y" >> $config_host_mak
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fi
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if test "$getauxval" = "yes" ; then
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echo "CONFIG_GETAUXVAL=y" >> $config_host_mak
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fi
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if test "$glusterfs" = "yes" ; then
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echo "CONFIG_GLUSTERFS=y" >> $config_host_mak
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fi
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1
disas.c
1
disas.c
@ -325,6 +325,7 @@ void disas(FILE *out, void *code, unsigned long size)
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s.info.mach = bfd_mach_x86_64;
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print_insn = print_insn_i386;
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#elif defined(_ARCH_PPC)
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s.info.disassembler_options = (char *)"any";
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print_insn = print_insn_ppc;
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#elif defined(__alpha__)
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print_insn = print_insn_alpha;
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File diff suppressed because it is too large
Load Diff
@ -67,53 +67,55 @@ typedef enum {
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#define TCG_TARGET_STACK_ALIGN 16
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#define TCG_TARGET_CALL_STACK_OFFSET 48
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/* optional instructions automatically implemented */
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#define TCG_TARGET_HAS_ext8u_i32 0 /* andi */
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#define TCG_TARGET_HAS_ext16u_i32 0
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#define TCG_TARGET_HAS_ext8u_i64 0
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#define TCG_TARGET_HAS_ext16u_i64 0
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#define TCG_TARGET_HAS_ext32u_i64 0
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_rot_i32 0
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 0
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#define TCG_TARGET_HAS_ext16u_i32 0
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#define TCG_TARGET_HAS_bswap16_i32 0
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#define TCG_TARGET_HAS_bswap32_i32 0
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_andc_i32 0
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_deposit_i32 0
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#define TCG_TARGET_HAS_movcond_i32 0
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 1
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#define TCG_TARGET_HAS_eqv_i32 1
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#define TCG_TARGET_HAS_nand_i32 1
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#define TCG_TARGET_HAS_nor_i32 1
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 0
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#define TCG_TARGET_HAS_muls2_i32 0
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rot_i64 0
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 0
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#define TCG_TARGET_HAS_ext16u_i64 0
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_bswap16_i64 0
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#define TCG_TARGET_HAS_bswap32_i64 0
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#define TCG_TARGET_HAS_bswap64_i64 0
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_andc_i64 0
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#define TCG_TARGET_HAS_orc_i64 0
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#define TCG_TARGET_HAS_eqv_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_deposit_i64 0
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#define TCG_TARGET_HAS_movcond_i64 0
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#define TCG_TARGET_HAS_add2_i64 0
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#define TCG_TARGET_HAS_sub2_i64 0
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#define TCG_TARGET_HAS_mulu2_i64 0
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#define TCG_TARGET_HAS_muls2_i64 0
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#define TCG_TARGET_HAS_andc_i64 1
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#define TCG_TARGET_HAS_orc_i64 1
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#define TCG_TARGET_HAS_eqv_i64 1
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#define TCG_TARGET_HAS_nand_i64 1
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#define TCG_TARGET_HAS_nor_i64 1
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 1
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#define TCG_TARGET_HAS_muls2_i64 1
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#define TCG_AREG0 TCG_REG_R27
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