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pc,pci,virtio: fixes, features

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Fixes all over the place.
 PXB support for ARM.
 boot index for vhost-user-fs.
 
 Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging

pc,pci,virtio: fixes, features

Fixes all over the place.
PXB support for ARM.
boot index for vhost-user-fs.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Sun 17 Jan 2021 11:44:55 GMT
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* remotes/mst/tags/for_upstream:
  acpi: Update _DSM method in expected files
  acpi: Enable pxb unit-test for ARM virt machine
  Kconfig: Compile PXB for ARM_VIRT
  acpi/gpex: Exclude pxb's resources from PCI0
  acpi/gpex: Inform os to keep firmware resource map
  acpi: Add addr offset in build_crs
  acpi: Fix unmatched expected DSDT.pxb file
  acpi: Allow DSDT acpi table changes
  vhost-user-fs: add the "bootindex" property
  pci/shpc: don't push attention button when ejecting powered-off device

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-01-17 17:04:40 +00:00
commit e0cbcf1eea
15 changed files with 94 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
hw/acpi/aml-build.c
View File

@ -2076,7 +2076,9 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL, NULL);
}
Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset,
uint32_t mmio32_offset, uint64_t mmio64_offset,
uint16_t bus_nr_offset)
{
Aml *crs = aml_resource_template();
CrsRangeSet temp_range_set;
@ -2189,10 +2191,10 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
for (i = 0; i < temp_range_set.io_ranges->len; i++) {
entry = g_ptr_array_index(temp_range_set.io_ranges, i);
aml_append(crs,
aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
AML_POS_DECODE, AML_ENTIRE_RANGE,
0, entry->base, entry->limit, 0,
entry->limit - entry->base + 1));
aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED,
AML_POS_DECODE, AML_ENTIRE_RANGE,
0, entry->base, entry->limit, io_offset,
entry->limit - entry->base + 1));
crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
}
@ -2205,7 +2207,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
AML_MAX_FIXED, AML_NON_CACHEABLE,
AML_READ_WRITE,
0, entry->base, entry->limit, 0,
0, entry->base, entry->limit, mmio32_offset,
entry->limit - entry->base + 1));
crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
}
@ -2217,7 +2219,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
AML_MAX_FIXED, AML_NON_CACHEABLE,
AML_READ_WRITE,
0, entry->base, entry->limit, 0,
0, entry->base, entry->limit, mmio64_offset,
entry->limit - entry->base + 1));
crs_range_insert(range_set->mem_64bit_ranges,
entry->base, entry->limit);
@ -2230,7 +2232,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
0,
pci_bus_num(host->bus),
max_bus,
0,
bus_nr_offset,
max_bus - pci_bus_num(host->bus) + 1));
return crs;

3
hw/i386/acpi-build.c
View File

@ -1360,7 +1360,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
}
aml_append(dev, build_prt(false));
crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
0, 0, 0, 0);
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(scope, dev);
aml_append(dsdt, scope);

2
hw/pci-bridge/Kconfig
View File

@ -5,7 +5,7 @@ config PCIE_PORT
config PXB
bool
default y if Q35
default y if Q35 || ARM_VIRT
config XIO3130
bool

87
hw/pci-host/gpex-acpi.c
View File

@ -112,10 +112,26 @@ static void acpi_dsdt_add_pci_osc(Aml *dev)
UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
ifctx = aml_if(aml_equal(aml_arg(0), UUID));
ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
uint8_t byte_list[1] = {1};
buf = aml_buffer(1, byte_list);
uint8_t byte_list[] = {
0x1 << 0 /* support for functions other than function 0 */ |
0x1 << 5 /* support for function 5 */
};
buf = aml_buffer(ARRAY_SIZE(byte_list), byte_list);
aml_append(ifctx1, aml_return(buf));
aml_append(ifctx, ifctx1);
/*
* PCI Firmware Specification 3.1
* 4.6.5. _DSM for Ignoring PCI Boot Configurations
*/
/* Arg2: Function Index: 5 */
ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(5)));
/*
* 0 - The operating system must not ignore the PCI configuration that
* firmware has done at boot time.
*/
aml_append(ifctx1, aml_return(aml_int(0)));
aml_append(ifctx, ifctx1);
aml_append(method, ifctx);
byte_list[0] = 0;
@ -130,6 +146,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
Aml *method, *crs, *dev, *rbuf;
PCIBus *bus = cfg->bus;
CrsRangeSet crs_range_set;
CrsRangeEntry *entry;
int i;
/* start to construct the tables for pxb */
crs_range_set_init(&crs_range_set);
@ -168,7 +186,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
* 1. The resources the pci-brige/pcie-root-port need.
* 2. The resources the devices behind pxb need.
*/
crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
cfg->pio.base, 0, 0, 0);
aml_append(dev, aml_name_decl("_CRS", crs));
acpi_dsdt_add_pci_osc(dev);
@ -176,7 +195,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(scope, dev);
}
}
crs_range_set_free(&crs_range_set);
/* tables for the main */
dev = aml_device("%s", "PCI0");
@ -194,36 +212,55 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(method, aml_return(aml_int(cfg->ecam.base)));
aml_append(dev, method);
/*
* At this point crs_range_set has all the ranges used by pci
* busses *other* than PCI0. These ranges will be excluded from
* the PCI0._CRS.
*/
rbuf = aml_resource_template();
aml_append(rbuf,
aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
nr_pcie_buses));
if (cfg->mmio32.size) {
aml_append(rbuf,
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
cfg->mmio32.base,
cfg->mmio32.base + cfg->mmio32.size - 1,
0x0000,
cfg->mmio32.size));
crs_replace_with_free_ranges(crs_range_set.mem_ranges,
cfg->mmio32.base,
cfg->mmio32.base + cfg->mmio32.size - 1);
for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
aml_append(rbuf,
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
entry->base, entry->limit,
0x0000, entry->limit - entry->base + 1));
}
}
if (cfg->pio.size) {
aml_append(rbuf,
aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
AML_ENTIRE_RANGE, 0x0000, 0x0000,
cfg->pio.size - 1,
cfg->pio.base,
cfg->pio.size));
crs_replace_with_free_ranges(crs_range_set.io_ranges,
0x0000,
cfg->pio.size - 1);
for (i = 0; i < crs_range_set.io_ranges->len; i++) {
entry = g_ptr_array_index(crs_range_set.io_ranges, i);
aml_append(rbuf,
aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
AML_ENTIRE_RANGE, 0x0000, entry->base,
entry->limit, cfg->pio.base,
entry->limit - entry->base + 1));
}
}
if (cfg->mmio64.size) {
aml_append(rbuf,
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
cfg->mmio64.base,
cfg->mmio64.base + cfg->mmio64.size - 1,
0x0000,
cfg->mmio64.size));
crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
cfg->mmio64.base,
cfg->mmio64.base + cfg->mmio64.size - 1);
for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
aml_append(rbuf,
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
entry->base,
entry->limit, 0x0000,
entry->limit - entry->base + 1));
}
}
aml_append(dev, aml_name_decl("_CRS", rbuf));
@ -242,4 +279,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(dev_res0, aml_name_decl("_CRS", crs));
aml_append(dev, dev_res0);
aml_append(scope, dev);
crs_range_set_free(&crs_range_set);
}

4
hw/pci/shpc.c
View File

@ -300,7 +300,6 @@ static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
SHPC_SLOT_STATUS_PRSNT_MASK);
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
SHPC_SLOT_EVENT_BUTTON |
SHPC_SLOT_EVENT_MRL |
SHPC_SLOT_EVENT_PRESENCE;
}
@ -566,7 +565,6 @@ void shpc_device_unplug_request_cb(HotplugHandler *hotplug_dev,
return;
}
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
@ -577,6 +575,8 @@ void shpc_device_unplug_request_cb(HotplugHandler *hotplug_dev,
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
SHPC_SLOT_EVENT_MRL |
SHPC_SLOT_EVENT_PRESENCE;
} else {
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
}
shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
shpc_interrupt_update(pci_hotplug_dev);

2
hw/virtio/vhost-user-fs-pci.c
View File

@ -68,6 +68,8 @@ static void vhost_user_fs_pci_instance_init(Object *obj)
virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
TYPE_VHOST_USER_FS);
object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
"bootindex");
}
static const VirtioPCIDeviceTypeInfo vhost_user_fs_pci_info = {

10
hw/virtio/vhost-user-fs.c
View File

@ -22,6 +22,7 @@
#include "qemu/error-report.h"
#include "hw/virtio/vhost-user-fs.h"
#include "monitor/monitor.h"
#include "sysemu/sysemu.h"
static void vuf_get_config(VirtIODevice *vdev, uint8_t *config)
{
@ -279,6 +280,14 @@ static Property vuf_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
static void vuf_instance_init(Object *obj)
{
VHostUserFS *fs = VHOST_USER_FS(obj);
device_add_bootindex_property(obj, &fs->bootindex, "bootindex",
"/filesystem@0", DEVICE(obj));
}
static void vuf_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -300,6 +309,7 @@ static const TypeInfo vuf_info = {
.name = TYPE_VHOST_USER_FS,
.parent = TYPE_VIRTIO_DEVICE,
.instance_size = sizeof(VHostUserFS),
.instance_init = vuf_instance_init,
.class_init = vuf_class_init,
};

4
include/hw/acpi/aml-build.h
View File

@ -452,7 +452,9 @@ void crs_replace_with_free_ranges(GPtrArray *ranges,
void crs_range_set_init(CrsRangeSet *range_set);
void crs_range_set_free(CrsRangeSet *range_set);
Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set);
Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset,
uint32_t mmio32_offset, uint64_t mmio64_offset,
uint16_t bus_nr_offset);
void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
uint64_t len, int node, MemoryAffinityFlags flags);

1
include/hw/virtio/vhost-user-fs.h
View File

@ -39,6 +39,7 @@ struct VHostUserFS {
VhostUserState vhost_user;
VirtQueue **req_vqs;
VirtQueue *hiprio_vq;
int32_t bootindex;
/*< public >*/
};

BIN
tests/data/acpi/microvm/DSDT.pcie
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Binary file not shown.

BIN
tests/data/acpi/virt/DSDT
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Binary file not shown.

BIN
tests/data/acpi/virt/DSDT.memhp
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Binary file not shown.

BIN
tests/data/acpi/virt/DSDT.numamem
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Binary file not shown.

BIN
tests/data/acpi/virt/DSDT.pxb
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Binary file not shown.

4
tests/qtest/bios-tables-test.c
View File

@ -1196,7 +1196,6 @@ static void test_acpi_virt_tcg_numamem(void)
}
#ifdef CONFIG_PXB
static void test_acpi_virt_tcg_pxb(void)
{
test_data data = {
@ -1228,7 +1227,6 @@ static void test_acpi_virt_tcg_pxb(void)
free_test_data(&data);
}
#endif
static void test_acpi_tcg_acpi_hmat(const char *machine)
{
@ -1342,9 +1340,7 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem);
qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
#ifdef CONFIG_PXB
qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
#endif
}
ret = g_test_run();
boot_sector_cleanup(disk);