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target/riscv: add support for Zcb extension

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Add encode and trans* functions support for Zcb instructions.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-03-07 16:13:58 +08:00 committed by Alistair Francis
parent c4935b5842
commit e0a3054f18
3 changed files with 125 additions and 0 deletions
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23
target/riscv/insn16.decode
View File

@ -43,6 +43,8 @@
%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
%imm_lui 12:s1 2:5 !function=ex_shift_12
%uimm_cl_b 5:1 6:1
%uimm_cl_h 5:1 !function=ex_shift_1
# Argument sets imported from insn32.decode:
&empty !extern
@ -53,6 +55,7 @@
&b imm rs2 rs1 !extern
&u imm rd !extern
&shift shamt rs1 rd !extern
&r2 rd rs1 !extern
# Formats 16:
@ -89,6 +92,12 @@
@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
@cu ... ... ... .. ... .. &r2 rs1=%rs1_3 rd=%rs1_3
@cl_b ... . .. ... .. ... .. &i imm=%uimm_cl_b rs1=%rs1_3 rd=%rs2_3
@cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3
@cs_b ... . .. ... .. ... .. &s imm=%uimm_cl_b rs1=%rs1_3 rs2=%rs2_3
@cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3
# *** RV32/64C Standard Extension (Quadrant 0) ***
{
# Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
@ -180,3 +189,17 @@ sw 110 . ..... ..... 10 @c_swsp
sd 111 . ..... ..... 10 @c_sdsp
c_fsw 111 . ..... ..... 10 @c_swsp
}
# *** RV64 and RV32 Zcb Extension ***
c_zext_b 100 111 ... 11 000 01 @cu
c_sext_b 100 111 ... 11 001 01 @cu
c_zext_h 100 111 ... 11 010 01 @cu
c_sext_h 100 111 ... 11 011 01 @cu
c_zext_w 100 111 ... 11 100 01 @cu
c_not 100 111 ... 11 101 01 @cu
c_mul 100 111 ... 10 ... 01 @cs_2
c_lbu 100 000 ... .. ... 00 @cl_b
c_lhu 100 001 ... 0. ... 00 @cl_h
c_lh 100 001 ... 1. ... 00 @cl_h
c_sb 100 010 ... .. ... 00 @cs_b
c_sh 100 011 ... 0. ... 00 @cs_h

100
target/riscv/insn_trans/trans_rvzce.c.inc Normal file
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@ -0,0 +1,100 @@
/*
* RISC-V translation routines for the Zcb Standard Extension.
*
* Copyright (c) 2021-2022 PLCT Lab
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define REQUIRE_ZCB(ctx) do { \
if (!ctx->cfg_ptr->ext_zcb) \
return false; \
} while (0)
static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a)
{
REQUIRE_ZCB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8u_tl);
}
static bool trans_c_zext_h(DisasContext *ctx, arg_c_zext_h *a)
{
REQUIRE_ZCB(ctx);
REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
}
static bool trans_c_sext_b(DisasContext *ctx, arg_c_sext_b *a)
{
REQUIRE_ZCB(ctx);
REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
}
static bool trans_c_sext_h(DisasContext *ctx, arg_c_sext_h *a)
{
REQUIRE_ZCB(ctx);
REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
}
static bool trans_c_zext_w(DisasContext *ctx, arg_c_zext_w *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZCB(ctx);
REQUIRE_ZBA(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext32u_tl);
}
static bool trans_c_not(DisasContext *ctx, arg_c_not *a)
{
REQUIRE_ZCB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_not_tl);
}
static bool trans_c_mul(DisasContext *ctx, arg_c_mul *a)
{
REQUIRE_ZCB(ctx);
REQUIRE_M_OR_ZMMUL(ctx);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL);
}
static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a)
{
REQUIRE_ZCB(ctx);
return gen_load(ctx, a, MO_UB);
}
static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a)
{
REQUIRE_ZCB(ctx);
return gen_load(ctx, a, MO_UW);
}
static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a)
{
REQUIRE_ZCB(ctx);
return gen_load(ctx, a, MO_SW);
}
static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a)
{
REQUIRE_ZCB(ctx);
return gen_store(ctx, a, MO_UB);
}
static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a)
{
REQUIRE_ZCB(ctx);
return gen_store(ctx, a, MO_UW);
}

2
target/riscv/translate.c
View File

@ -1091,6 +1091,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
#include "insn_trans/trans_rvzce.c.inc"
/* Include decoders for factored-out extensions */
#include "decode-XVentanaCondOps.c.inc"