pseries: Fix some small errors in XICS logic
Under certain circumstances the emulation for the pseries "XICS" interrupt controller was clearing a pending interrupt from the XISR register, without also clearing the corresponding priority variable. This will cause problems later when can trigger sanity checks in the under-development in-kernel XICS implementation. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -101,6 +101,7 @@ static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
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if (XISR(ss) && (cppr <= ss->pending_priority)) {
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old_xisr = XISR(ss);
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ss->xirr &= ~XISR_MASK; /* Clear XISR */
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ss->pending_priority = 0xff;
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qemu_irq_lower(ss->output);
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ics_reject(icp->ics, old_xisr);
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}
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@ -127,6 +128,7 @@ static uint32_t icp_accept(struct icp_server_state *ss)
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qemu_irq_lower(ss->output);
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ss->xirr = ss->pending_priority << 24;
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ss->pending_priority = 0xff;
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trace_xics_icp_accept(xirr, ss->xirr);
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