e500: Adding CCSR memory region
All devices are also placed under CCSR memory region. The CCSR memory region is exported to pci device. The MSI interrupt generation is the main reason to export the CCSR region to PCI device. This put the requirement to move mpic under CCSR region, but logically all devices should be under CCSR. So this patch places all emulated devices under ccsr region. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Bharat Bhushan
Alexander Graf
parent
4fd50339c0
commit
dffb1dc29f
@ -46,13 +46,15 @@
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/* TODO: parameterize */
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#define MPC8544_CCSRBAR_BASE 0xE0000000ULL
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#define MPC8544_CCSRBAR_SIZE 0x00100000ULL
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#define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000ULL)
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#define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500ULL)
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#define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600ULL)
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#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000ULL)
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#define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
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#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
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#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
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#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
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#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \
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MPC8544_PCI_REGS_OFFSET)
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#define MPC8544_PCI_REGS_SIZE 0x1000ULL
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#define MPC8544_PCI_IO 0xE1000000ULL
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#define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000ULL)
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#define MPC8544_UTIL_OFFSET 0xe0000ULL
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#define MPC8544_SPIN_BASE 0xEF000000ULL
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struct boot_info
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@ -267,13 +269,12 @@ static int ppce500_load_device_tree(CPUPPCState *env,
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/* XXX should contain a reasonable value */
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qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
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snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc,
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MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE);
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snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
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qemu_devtree_add_subnode(fdt, mpic);
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qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
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qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic");
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qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_BASE -
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MPC8544_CCSRBAR_BASE, 0x40000);
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qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
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0x40000);
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qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
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qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
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mpic_ph = qemu_devtree_alloc_phandle(fdt);
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@ -286,17 +287,16 @@ static int ppce500_load_device_tree(CPUPPCState *env,
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* device it finds in the dt as serial output device. And we generate
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* devices in reverse order to the dt.
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*/
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dt_serial_create(fdt, MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE,
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dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
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soc, mpic, "serial1", 1, false);
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dt_serial_create(fdt, MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE,
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dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
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soc, mpic, "serial0", 0, true);
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snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
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MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE);
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MPC8544_UTIL_OFFSET);
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qemu_devtree_add_subnode(fdt, gutil);
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qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
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qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_BASE -
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MPC8544_CCSRBAR_BASE, 0x1000);
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qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
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qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
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snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
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@ -422,6 +422,8 @@ void ppce500_init(PPCE500Params *params)
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qemu_irq **irqs, *mpic;
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DeviceState *dev;
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CPUPPCState *firstenv = NULL;
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MemoryRegion *ccsr;
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SysBusDevice *s;
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/* Setup CPUs */
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if (params->cpu_model == NULL) {
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@ -450,7 +452,8 @@ void ppce500_init(PPCE500Params *params)
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irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
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irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
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env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
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env->mpic_cpu_base = MPC8544_MPIC_REGS_BASE + 0x20000;
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env->mpic_cpu_base = MPC8544_CCSRBAR_BASE +
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MPC8544_MPIC_REGS_OFFSET + 0x20000;
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ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
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@ -477,8 +480,12 @@ void ppce500_init(PPCE500Params *params)
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vmstate_register_ram_global(ram);
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memory_region_add_subregion(address_space_mem, 0, ram);
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ccsr = g_malloc0(sizeof(MemoryRegion));
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memory_region_init(ccsr, "e500-ccsr", MPC8544_CCSRBAR_SIZE);
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memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, ccsr);
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/* MPIC */
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mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE,
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mpic = mpic_init(ccsr, MPC8544_MPIC_REGS_OFFSET,
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smp_cpus, irqs, NULL);
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if (!mpic) {
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@ -487,25 +494,35 @@ void ppce500_init(PPCE500Params *params)
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/* Serial */
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if (serial_hds[0]) {
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serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE,
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serial_mm_init(ccsr, MPC8544_SERIAL0_REGS_OFFSET,
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0, mpic[12+26], 399193,
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serial_hds[0], DEVICE_BIG_ENDIAN);
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}
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if (serial_hds[1]) {
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serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE,
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serial_mm_init(ccsr, MPC8544_SERIAL1_REGS_OFFSET,
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0, mpic[12+26], 399193,
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serial_hds[1], DEVICE_BIG_ENDIAN);
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}
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/* General Utility device */
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sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL);
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dev = qdev_create(NULL, "mpc8544-guts");
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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memory_region_add_subregion(ccsr, MPC8544_UTIL_OFFSET,
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sysbus_mmio_get_region(s, 0));
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/* PCI */
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dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
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mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
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mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
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NULL);
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dev = qdev_create(NULL, "e500-pcihost");
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
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sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
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sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
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sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
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memory_region_add_subregion(ccsr, MPC8544_PCI_REGS_OFFSET,
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sysbus_mmio_get_region(s, 0));
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pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
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if (!pci_bus)
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printf("couldn't create PCI controller!\n");
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