tcg-ppc64: Merge ppc32 register usage
Good enough to run some instructions before things go awry. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -31,6 +31,16 @@
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# define TCG_TARGET_CALL_ALIGN_ARGS 1
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#endif
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/* For some memory operations, we need a scratch that isn't R0. For the AIX
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calling convention, we can re-use the TOC register since we'll be reloading
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it at every call. Otherwise R12 will do nicely as neither a call-saved
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register nor a parameter register. */
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#ifdef _CALL_AIX
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# define TCG_REG_TMP1 TCG_REG_R2
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#else
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# define TCG_REG_TMP1 TCG_REG_R12
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#endif
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/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
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#define SZP ((int)sizeof(void *))
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@ -119,6 +129,8 @@ static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_R31,
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TCG_REG_R12, /* call clobbered, non-arguments */
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TCG_REG_R11,
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TCG_REG_R2,
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TCG_REG_R13,
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TCG_REG_R10, /* call clobbered, arguments */
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TCG_REG_R9,
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TCG_REG_R8,
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@ -141,11 +153,12 @@ static const int tcg_target_call_iarg_regs[] = {
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};
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static const int tcg_target_call_oarg_regs[] = {
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TCG_REG_R3
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TCG_REG_R3,
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TCG_REG_R4
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};
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static const int tcg_target_callee_save_regs[] = {
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#ifdef __APPLE__
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#ifdef TCG_TARGET_CALL_DARWIN
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TCG_REG_R11,
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#endif
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TCG_REG_R14,
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@ -718,7 +731,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
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{
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tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
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bool is_store = false;
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TCGReg rs = TCG_REG_R2;
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TCGReg rs = TCG_REG_TMP1;
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switch (opi) {
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case LD: case LWA:
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@ -1184,7 +1197,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
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intptr_t diff = tcg_pcrel_diff(s, tgt);
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if (in_range_b(diff) && toc == (uint32_t)toc) {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, toc);
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
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tcg_out_b(s, LK, tgt);
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} else {
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/* Fold the low bits of the constant into the addresses below. */
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@ -1196,10 +1209,10 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
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} else {
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ofs = 0;
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}
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R2, ofs);
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
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tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_R2, ofs + SZP);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
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tcg_out32(s, BCCTR | BO_ALWAYS | LK);
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}
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#elif defined(_CALL_ELF) && _CALL_ELF == 2
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@ -1314,8 +1327,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits,
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QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
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tlb_table[NB_MMU_MODES - 1][1])
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> 0x7ff0 + 0x7fff);
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tcg_out32(s, ADDI | TAI(TCG_REG_R2, base, 0x7ff0));
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base = TCG_REG_R2;
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tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0));
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base = TCG_REG_TMP1;
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cmp_off -= 0x7ff0;
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add_off -= 0x7ff0;
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}
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@ -1335,9 +1348,9 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits,
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/* Load the tlb comparator. */
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
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tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_REG_R3, cmp_off + 4);
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tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
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} else {
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tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_R2, TCG_REG_R3, cmp_off);
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tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
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}
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/* Load the TLB addend for use on the fast path. Do this asap
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@ -1358,11 +1371,13 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits,
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}
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_R2, 0, 7, TCG_TYPE_I32);
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
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0, 7, TCG_TYPE_I32);
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tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
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tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
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} else {
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_R2, 0, 7, TCG_TYPE_TL);
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
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0, 7, TCG_TYPE_TL);
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}
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return addrlo;
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@ -1520,8 +1535,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
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#else /* !CONFIG_SOFTMMU */
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rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
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if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
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tcg_out_ext32u(s, TCG_REG_R2, addrlo);
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addrlo = TCG_REG_R2;
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tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
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addrlo = TCG_REG_TMP1;
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}
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#endif
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@ -1593,8 +1608,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
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#else /* !CONFIG_SOFTMMU */
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rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
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if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
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tcg_out_ext32u(s, TCG_REG_R2, addrlo);
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addrlo = TCG_REG_R2;
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tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
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addrlo = TCG_REG_TMP1;
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}
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#endif
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@ -1615,9 +1630,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
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uint32_t insn = qemu_stx_opc[opc];
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if (!HAVE_ISA_2_06 && insn == STDBRX) {
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tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
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tcg_out32(s, ADDI | TAI(TCG_REG_R2, addrlo, 4));
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tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
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tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
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tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_R2));
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tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
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} else {
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tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
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}
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@ -2428,11 +2443,13 @@ static void tcg_target_init(TCGContext *s)
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tcg_regset_clear(s->reserved_regs);
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* mem temp */
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#ifdef __APPLE__
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R11); /* ??? */
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#if defined(_CALL_SYSV)
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
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#endif
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#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
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#endif
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
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tcg_add_target_add_op_defs(ppc_op_defs);
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}
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