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Honor CPU_DUMP_FPU

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Merge remote-tracking branch 'remotes/rth/tags/pull-fpu-20180518' into staging

Honor CPU_DUMP_FPU

# gpg: Signature made Fri 18 May 2018 22:56:12 BST
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-fpu-20180518:
  target/xtensa: Honor CPU_DUMP_FPU
  target/unicore32: Honor CPU_DUMP_FPU
  target/sparc: Honor CPU_DUMP_FPU
  target/s390x: Honor CPU_DUMP_FPU
  target/riscv: Honor CPU_DUMP_FPU
  target/ppc: Honor CPU_DUMP_FPU
  target/mips: Honor CPU_DUMP_FPU
  target/alpha: Honor CPU_DUMP_FPU

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-05-21 09:44:37 +01:00
commit dfa93a0b6e
8 changed files with 57 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
target/alpha/helper.c
View File

@ -442,20 +442,19 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n",
env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8));
for (i = 0; i < 31; i++) {
cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,
linux_reg_names[i], cpu_alpha_load_gr(env, i));
if ((i % 3) == 2)
cpu_fprintf(f, "\n");
cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx "%c", i,
linux_reg_names[i], cpu_alpha_load_gr(env, i),
(i % 3) == 2 ? '\n' : ' ');
}
cpu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n",
env->lock_addr, env->lock_value);
for (i = 0; i < 31; i++) {
cpu_fprintf(f, "FIR%02d " TARGET_FMT_lx " ", i,
*((uint64_t *)(&env->fir[i])));
if ((i % 3) == 2)
cpu_fprintf(f, "\n");
if (flags & CPU_DUMP_FPU) {
for (i = 0; i < 31; i++) {
cpu_fprintf(f, "FIR%02d %016" PRIx64 "%c", i, env->fir[i],
(i % 3) == 2 ? '\n' : ' ');
}
}
cpu_fprintf(f, "\n");
}

3
target/mips/translate.c
View File

@ -20446,8 +20446,9 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
env->CP0_Config2, env->CP0_Config3);
cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
env->CP0_Config4, env->CP0_Config5);
if (env->hflags & MIPS_HFLAG_FPU)
if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
fpu_dump_state(env, f, cpu_fprintf, flags);
}
}
void mips_tcg_init(void)

20
target/ppc/translate.c
View File

@ -7048,14 +7048,20 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
}
cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
env->reserve_addr);
for (i = 0; i < 32; i++) {
if ((i & (RFPL - 1)) == 0)
cpu_fprintf(f, "FPR%02d", i);
cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
if ((i & (RFPL - 1)) == (RFPL - 1))
cpu_fprintf(f, "\n");
if (flags & CPU_DUMP_FPU) {
for (i = 0; i < 32; i++) {
if ((i & (RFPL - 1)) == 0) {
cpu_fprintf(f, "FPR%02d", i);
}
cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
if ((i & (RFPL - 1)) == (RFPL - 1)) {
cpu_fprintf(f, "\n");
}
}
cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
}
cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
#if !defined(CONFIG_USER_ONLY)
cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
" PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",

12
target/riscv/cpu.c
View File

@ -219,11 +219,13 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
cpu_fprintf(f, "\n");
}
}
for (i = 0; i < 32; i++) {
cpu_fprintf(f, " %s %016" PRIx64,
riscv_fpr_regnames[i], env->fpr[i]);
if ((i & 3) == 3) {
cpu_fprintf(f, "\n");
if (flags & CPU_DUMP_FPU) {
for (i = 0; i < 32; i++) {
cpu_fprintf(f, " %s %016" PRIx64,
riscv_fpr_regnames[i], env->fpr[i]);
if ((i & 3) == 3) {
cpu_fprintf(f, "\n");
}
}
}
}

23
target/s390x/helper.c
View File

@ -327,21 +327,22 @@ void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
}
}
for (i = 0; i < 16; i++) {
cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll);
if ((i % 4) == 3) {
cpu_fprintf(f, "\n");
if (flags & CPU_DUMP_FPU) {
if (s390_has_feat(S390_FEAT_VECTOR)) {
for (i = 0; i < 32; i++) {
cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64 "%c",
i, env->vregs[i][0].ll, env->vregs[i][1].ll,
i % 2 ? '\n' : ' ');
}
} else {
cpu_fprintf(f, " ");
for (i = 0; i < 16; i++) {
cpu_fprintf(f, "F%02d=%016" PRIx64 "%c",
i, get_freg(env, i)->ll,
(i % 4) == 3 ? '\n' : ' ');
}
}
}
for (i = 0; i < 32; i++) {
cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i,
env->vregs[i][0].ll, env->vregs[i][1].ll);
cpu_fprintf(f, (i % 2) ? "\n" : " ");
}
#ifndef CONFIG_USER_ONLY
for (i = 0; i < 16; i++) {
cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);

17
target/sparc/cpu.c
View File

@ -647,15 +647,18 @@ void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
}
}
for (i = 0; i < TARGET_DPREGS; i++) {
if ((i & 3) == 0) {
cpu_fprintf(f, "%%f%02d: ", i * 2);
}
cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
if ((i & 3) == 3) {
cpu_fprintf(f, "\n");
if (flags & CPU_DUMP_FPU) {
for (i = 0; i < TARGET_DPREGS; i++) {
if ((i & 3) == 0) {
cpu_fprintf(f, "%%f%02d: ", i * 2);
}
cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
if ((i & 3) == 3) {
cpu_fprintf(f, "\n");
}
}
}
#ifdef TARGET_SPARC64
cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
(unsigned)cpu_get_ccr(env));

4
target/unicore32/translate.c
View File

@ -2101,7 +2101,9 @@ void uc32_cpu_dump_state(CPUState *cs, FILE *f,
psr & (1 << 28) ? 'V' : '-',
cpu_mode_names[psr & 0xf]);
cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
if (flags & CPU_DUMP_FPU) {
cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
}
}
void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb,

3
target/xtensa/translate.c
View File

@ -1243,7 +1243,8 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
}
}
if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
if ((flags & CPU_DUMP_FPU) &&
xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
cpu_fprintf(f, "\n");
for (i = 0; i < 16; ++i) {