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target-tricore: Added new JNE instruction variant

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If D[15] is != sign_ext(const4) then PC will be set to (PC +
zero_ext(disp4 + 16)).

[BK: fixed style errors]
Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
Message-Id: <1465314555-11501-5-git-send-email-peer.adelt@c-lab.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Peer Adelt 2016-06-07 17:49:15 +02:00 committed by Bastian Koppelmann
parent 550929dd46
commit dedd8c9c32
2 changed files with 20 additions and 0 deletions
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18
target/tricore/translate.c
View File

@ -3362,9 +3362,17 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
case OPC1_16_SBC_JEQ: case OPC1_16_SBC_JEQ:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
break; break;
case OPC1_16_SBC_JEQ2:
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant,
offset + 16);
break;
case OPC1_16_SBC_JNE: case OPC1_16_SBC_JNE:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
break; break;
case OPC1_16_SBC_JNE2:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15],
constant, offset + 16);
break;
/* SBRN-format jumps */ /* SBRN-format jumps */
case OPC1_16_SBRN_JZ_T: case OPC1_16_SBRN_JZ_T:
temp = tcg_temp_new(); temp = tcg_temp_new();
@ -4097,6 +4105,16 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, const16, address); gen_compute_branch(ctx, op1, 0, 0, const16, address);
break; break;
case OPC1_16_SBC_JEQ2:
case OPC1_16_SBC_JNE2:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
address = MASK_OP_SBC_DISP4(ctx->opcode);
const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, const16, address);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
/* SBRN-format */ /* SBRN-format */
case OPC1_16_SBRN_JNZ_T: case OPC1_16_SBRN_JNZ_T:
case OPC1_16_SBRN_JZ_T: case OPC1_16_SBRN_JZ_T:

2
target/tricore/tricore-opcodes.h
View File

@ -311,6 +311,7 @@ enum {
OPC1_16_SRR_EQ = 0x3a, OPC1_16_SRR_EQ = 0x3a,
OPC1_16_SB_J = 0x3c, OPC1_16_SB_J = 0x3c,
OPC1_16_SBC_JEQ = 0x1e, OPC1_16_SBC_JEQ = 0x1e,
OPC1_16_SBC_JEQ2 = 0x9e,
OPC1_16_SBR_JEQ = 0x3e, OPC1_16_SBR_JEQ = 0x3e,
OPC1_16_SBR_JGEZ = 0xce, OPC1_16_SBR_JGEZ = 0xce,
OPC1_16_SBR_JGTZ = 0x4e, OPC1_16_SBR_JGTZ = 0x4e,
@ -318,6 +319,7 @@ enum {
OPC1_16_SBR_JLEZ = 0x8e, OPC1_16_SBR_JLEZ = 0x8e,
OPC1_16_SBR_JLTZ = 0x0e, OPC1_16_SBR_JLTZ = 0x0e,
OPC1_16_SBC_JNE = 0x5e, OPC1_16_SBC_JNE = 0x5e,
OPC1_16_SBC_JNE2 = 0xde,
OPC1_16_SBR_JNE = 0x7e, OPC1_16_SBR_JNE = 0x7e,
OPC1_16_SB_JNZ = 0xee, OPC1_16_SB_JNZ = 0xee,
OPC1_16_SBR_JNZ = 0xf6, OPC1_16_SBR_JNZ = 0xf6,