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target-arm queue:

Browse Source 
* More refactoring of files into tcg/
  * Don't allow stage 2 page table walks to downgrade to NS
  * Fix handling of SW and NSW bits for stage 2 walks
  * MAINTAINERS: Update Akihiko Odaki's email address
  * ui: Fix pixel colour channel order for PNG screenshots
  * docs: Remove unused weirdly-named cross-reference targets
  * hw/mips/malta: Fix minor dead code issue
  * Fixes for the "allow CONFIG_TCG=n" changes
  * tests/qtest: Don't run cdrom boot tests if no accelerator is present
  * target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check
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Merge tag 'pull-target-arm-20230512' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * More refactoring of files into tcg/
 * Don't allow stage 2 page table walks to downgrade to NS
 * Fix handling of SW and NSW bits for stage 2 walks
 * MAINTAINERS: Update Akihiko Odaki's email address
 * ui: Fix pixel colour channel order for PNG screenshots
 * docs: Remove unused weirdly-named cross-reference targets
 * hw/mips/malta: Fix minor dead code issue
 * Fixes for the "allow CONFIG_TCG=n" changes
 * tests/qtest: Don't run cdrom boot tests if no accelerator is present
 * target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check

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# gpg: Signature made Fri 12 May 2023 04:32:51 PM BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]

* tag 'pull-target-arm-20230512' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check
  tests/qtest: Don't run cdrom boot tests if no accelerator is present
  target/arm: Select CONFIG_ARM_V7M when TCG is enabled
  target/arm: Select SEMIHOSTING when using TCG
  hw/mips/malta: Fix minor dead code issue
  docs: Remove unused weirdly-named cross-reference targets
  ui: Fix pixel colour channel order for PNG screenshots
  MAINTAINERS: Update Akihiko Odaki's email address
  target/arm: Fix handling of SW and NSW bits for stage 2 walks
  target/arm: Don't allow stage 2 page table walks to downgrade to NS
  target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/
  target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-05-13 07:36:55 +01:00
commit debca86cad
25 changed files with 109 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
MAINTAINERS
View File

@ -2566,7 +2566,7 @@ Core Audio framework backend
M: Gerd Hoffmann <kraxel@redhat.com>
M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Christian Schoenebeck <qemu_oss@crudebyte.com>
R: Akihiko Odaki <akihiko.odaki@gmail.com>
R: Akihiko Odaki <akihiko.odaki@daynix.com>
S: Odd Fixes
F: audio/coreaudio.c
@ -2850,7 +2850,7 @@ F: docs/devel/ui.rst
Cocoa graphics
M: Peter Maydell <peter.maydell@linaro.org>
M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Akihiko Odaki <akihiko.odaki@gmail.com>
R: Akihiko Odaki <akihiko.odaki@daynix.com>
S: Odd Fixes
F: ui/cocoa.m

2
docs/system/devices/igb.rst
View File

@ -29,7 +29,7 @@ Using igb
=========
Using igb should be nothing different from using another network device. See
:ref:`pcsys_005fnetwork` in general.
:ref:`Network_emulation` in general.
However, you may also need to perform additional steps to activate SR-IOV
feature on your guest. For Linux, refer to [4]_.

2
docs/system/devices/ivshmem.rst
View File

@ -1,5 +1,3 @@
.. _pcsys_005fivshmem:
Inter-VM Shared Memory device
-----------------------------

2
docs/system/devices/net.rst
View File

@ -1,4 +1,4 @@
.. _pcsys_005fnetwork:
.. _Network_Emulation:
Network emulation
-----------------

2
docs/system/devices/usb.rst
View File

@ -1,5 +1,3 @@
.. _pcsys_005fusb:
USB emulation
-------------

2
docs/system/keys.rst
View File

@ -1,4 +1,4 @@
.. _pcsys_005fkeys:
.. _GUI_keys:
Keys in the graphical frontends
-------------------------------

2
docs/system/linuxboot.rst
View File

@ -27,4 +27,4 @@ virtual serial port and the QEMU monitor to the console with the
-append "root=/dev/hda console=ttyS0" -nographic
Use Ctrl-a c to switch between the serial console and the monitor (see
:ref:`pcsys_005fkeys`).
:ref:`GUI_keys`).

4
docs/system/target-i386.rst
View File

@ -3,8 +3,6 @@
x86 System emulator
-------------------
.. _pcsys_005fdevices:
Board-specific documentation
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@ -32,8 +30,6 @@ Architectural features
i386/sgx
i386/amd-memory-encryption
.. _pcsys_005freq:
OS requirements
~~~~~~~~~~~~~~~

5
hw/mips/malta.c
View File

@ -748,7 +748,6 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
uint64_t kernel_entry)
{
uint32_t *p;
void *v;
/* Small bootloader */
p = (uint32_t *)base;
@ -785,9 +784,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
*
*/
v = p;
bl_setup_gt64120_jump_kernel(&v, run_addr, kernel_entry);
p = v;
bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
/* YAMON subroutines */
p = (uint32_t *) (base + 0x800);

9
target/arm/Kconfig
View File

@ -1,13 +1,8 @@
config ARM
bool
select ARM_COMPATIBLE_SEMIHOSTING if TCG
select ARM_V7M if TCG
config AARCH64
bool
select ARM
# This config exists just so we can make SEMIHOSTING default when TCG
# is selected without also changing it for other architectures.
config ARM_SEMIHOSTING
bool
default y if TCG && ARM
select ARM_COMPATIBLE_SEMIHOSTING

2
target/arm/gdbstub64.c
View File

@ -233,7 +233,7 @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
ARMVAParameters param;
param = aa64_va_parameters(env, -is_high, mmu_idx, is_data);
param = aa64_va_parameters(env, -is_high, mmu_idx, is_data, false);
return gdb_get_reg64(buf, pauth_ptr_mask(param));
}
default:

15
target/arm/helper.c
View File

@ -4904,7 +4904,7 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
unsigned int page_size_granule, page_shift, num, scale, exponent;
/* Extract one bit to represent the va selector in use. */
uint64_t select = sextract64(value, 36, 1);
ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true);
ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true, false);
TLBIRange ret = { };
ARMGranuleSize gran;
@ -11193,7 +11193,8 @@ static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran,
}
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
ARMMMUIdx mmu_idx, bool data)
ARMMMUIdx mmu_idx, bool data,
bool el1_is_aa32)
{
uint64_t tcr = regime_tcr(env, mmu_idx);
bool epd, hpd, tsz_oob, ds, ha, hd;
@ -11289,6 +11290,16 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
}
}
if (stage2 && el1_is_aa32) {
/*
* For AArch32 EL1 the min txsz (and thus max IPA size) requirements
* are loosened: a configured IPA of 40 bits is permitted even if
* the implemented PA is less than that (and so a 40 bit IPA would
* fault for an AArch64 EL1). See R_DTLMN.
*/
min_tsz = MIN(min_tsz, 24);
}
if (tsz > max_tsz) {
tsz = max_tsz;
tsz_oob = true;

8
target/arm/helper.h
View File

@ -1039,9 +1039,9 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#include "helper-sve.h"
#include "helper-sme.h"
#include "tcg/helper-a64.h"
#include "tcg/helper-sve.h"
#include "tcg/helper-sme.h"
#endif
#include "helper-mve.h"
#include "tcg/helper-mve.h"

12
target/arm/internals.h
View File

@ -1091,8 +1091,18 @@ typedef struct ARMVAParameters {
ARMGranuleSize gran : 2;
} ARMVAParameters;
/**
* aa64_va_parameters: Return parameters for an AArch64 virtual address
* @env: CPU
* @va: virtual address to look up
* @mmu_idx: determines translation regime to use
* @data: true if this is a data access
* @el1_is_aa32: true if we are asking about stage 2 when EL1 is AArch32
* (ignored if @mmu_idx is for a stage 1 regime; only affects tsz/tsz_oob)
*/
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
ARMMMUIdx mmu_idx, bool data);
ARMMMUIdx mmu_idx, bool data,
bool el1_is_aa32);
int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx);

95
target/arm/ptw.c
View File

@ -103,6 +103,37 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
return stage_1_mmu_idx(arm_mmu_idx(env));
}
/*
* Return where we should do ptw loads from for a stage 2 walk.
* This depends on whether the address we are looking up is a
* Secure IPA or a NonSecure IPA, which we know from whether this is
* Stage2 or Stage2_S.
* If this is the Secure EL1&0 regime we need to check the NSW and SW bits.
*/
static ARMMMUIdx ptw_idx_for_stage_2(CPUARMState *env, ARMMMUIdx stage2idx)
{
bool s2walk_secure;
/*
* We're OK to check the current state of the CPU here because
* (1) we always invalidate all TLBs when the SCR_EL3.NS bit changes
* (2) there's no way to do a lookup that cares about Stage 2 for a
* different security state to the current one for AArch64, and AArch32
* never has a secure EL2. (AArch32 ATS12NSO[UP][RW] allow EL3 to do
* an NS stage 1+2 lookup while the NS bit is 0.)
*/
if (!arm_is_secure_below_el3(env) || !arm_el_is_aa64(env, 3)) {
return ARMMMUIdx_Phys_NS;
}
if (stage2idx == ARMMMUIdx_Stage2_S) {
s2walk_secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
} else {
s2walk_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
}
return s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS;
}
static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx)
{
return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
@ -220,7 +251,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx;
uint8_t pte_attrs;
bool pte_secure;
ptw->out_virt = addr;
@ -232,8 +262,8 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
if (regime_is_stage2(s2_mmu_idx)) {
S1Translate s2ptw = {
.in_mmu_idx = s2_mmu_idx,
.in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS,
.in_secure = is_secure,
.in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
.in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
.in_debug = true,
};
GetPhysAddrResult s2 = { };
@ -244,12 +274,12 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
}
ptw->out_phys = s2.f.phys_addr;
pte_attrs = s2.cacheattrs.attrs;
pte_secure = s2.f.attrs.secure;
ptw->out_secure = s2.f.attrs.secure;
} else {
/* Regime is physical. */
ptw->out_phys = addr;
pte_attrs = 0;
pte_secure = is_secure;
ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S;
}
ptw->out_host = NULL;
ptw->out_rw = false;
@ -270,7 +300,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
ptw->out_rw = full->prot & PAGE_WRITE;
pte_attrs = full->pte_attrs;
pte_secure = full->attrs.secure;
ptw->out_secure = full->attrs.secure;
#else
g_assert_not_reached();
#endif
@ -293,11 +323,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
}
}
/* Check if page table walk is to secure or non-secure PA space. */
ptw->out_secure = (is_secure
&& !(pte_secure
? env->cp15.vstcr_el2 & VSTCR_SW
: env->cp15.vtcr_el2 & VTCR_NSW));
ptw->out_be = regime_translation_big_endian(env, mmu_idx);
return true;
@ -1109,17 +1134,6 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
sl0 = extract32(tcr, 6, 2);
if (is_aa64) {
/*
* AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of
* get_phys_addr_lpae, that used aa64_va_parameters which apply
* to aarch64. If Stage1 is aarch32, the min_txsz is larger.
* See AArch64.S2MinTxSZ, where min_tsz is 24, translated to
* inputsize is 64 - 24 = 40.
*/
if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) {
goto fail;
}
/*
* AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
* so interleave AArch64.S2StartLevel.
@ -1259,7 +1273,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
int ps;
param = aa64_va_parameters(env, address, mmu_idx,
access_type != MMU_INST_FETCH);
access_type != MMU_INST_FETCH,
!arm_el_is_aa64(env, 1));
level = 0;
/*
@ -1415,17 +1430,18 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
descaddrmask &= ~indexmask_grainsize;
/*
* Secure accesses start with the page table in secure memory and
* Secure stage 1 accesses start with the page table in secure memory and
* can be downgraded to non-secure at any step. Non-secure accesses
* remain non-secure. We implement this by just ORing in the NSTable/NS
* bits at each step.
* Stage 2 never gets this kind of downgrade.
*/
tableattrs = is_secure ? 0 : (1 << 4);
next_level:
descaddr |= (address >> (stride * (4 - level))) & indexmask;
descaddr &= ~7ULL;
nstable = extract32(tableattrs, 4, 1);
nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1);
if (nstable) {
/*
* Stage2_S -> Stage2 or Phys_S -> Phys_NS
@ -2725,7 +2741,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
hwaddr ipa;
int s1_prot, s1_lgpgsz;
bool is_secure = ptw->in_secure;
bool ret, ipa_secure, s2walk_secure;
bool ret, ipa_secure;
ARMCacheAttrs cacheattrs1;
bool is_el0;
uint64_t hcr;
@ -2739,20 +2755,11 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
ipa = result->f.phys_addr;
ipa_secure = result->f.attrs.secure;
if (is_secure) {
/* Select TCR based on the NS bit from the S1 walk. */
s2walk_secure = !(ipa_secure
? env->cp15.vstcr_el2 & VSTCR_SW
: env->cp15.vtcr_el2 & VTCR_NSW);
} else {
assert(!ipa_secure);
s2walk_secure = false;
}
is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
ptw->in_ptw_idx = s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS;
ptw->in_secure = s2walk_secure;
ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
ptw->in_secure = ipa_secure;
ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx);
/*
* S1 is done, now do S2 translation.
@ -2860,6 +2867,16 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
break;
case ARMMMUIdx_Stage2:
case ARMMMUIdx_Stage2_S:
/*
* Second stage lookup uses physical for ptw; whether this is S or
* NS may depend on the SW/NSW bits if this is a stage 2 lookup for
* the Secure EL2&0 regime.
*/
ptw->in_ptw_idx = ptw_idx_for_stage_2(env, mmu_idx);
break;
case ARMMMUIdx_E10_0:
s1_mmu_idx = ARMMMUIdx_Stage1_E0;
goto do_twostage;
@ -2883,7 +2900,7 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
/* fall through */
default:
/* Single stage and second stage uses physical for ptw. */
/* Single stage uses physical for ptw. */
ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS;
break;
}

0
target/arm/arm_ldst.h → target/arm/tcg/arm_ldst.h
View File

0
target/arm/helper-a64.h → target/arm/tcg/helper-a64.h
View File

0
target/arm/helper-mve.h → target/arm/tcg/helper-mve.h
View File

0
target/arm/helper-sme.h → target/arm/tcg/helper-sme.h
View File

0
target/arm/helper-sve.h → target/arm/tcg/helper-sve.h
View File

6
target/arm/tcg/pauth_helper.c
View File

@ -293,7 +293,7 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
ARMPACKey *key, bool data)
{
ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false);
uint64_t pac, ext_ptr, ext, test;
int bot_bit, top_bit;
@ -355,7 +355,7 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
ARMPACKey *key, bool data, int keynumber)
{
ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false);
int bot_bit, top_bit;
uint64_t pac, orig_ptr, test;
@ -379,7 +379,7 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data)
{
ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false);
return pauth_original_ptr(ptr, param);
}

0
target/arm/sve_ldst_internal.h → target/arm/tcg/sve_ldst_internal.h
View File

0
target/arm/translate-a32.h → target/arm/tcg/translate-a32.h
View File

10
tests/qtest/cdrom-test.c
View File

@ -130,6 +130,11 @@ static void test_cdboot(gconstpointer data)
static void add_x86_tests(void)
{
if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) {
g_test_skip("No KVM or TCG accelerator available, skipping boot tests");
return;
}
qtest_add_data_func("cdrom/boot/default", "-cdrom ", test_cdboot);
qtest_add_data_func("cdrom/boot/virtio-scsi",
"-device virtio-scsi -device scsi-cd,drive=cdr "
@ -176,6 +181,11 @@ static void add_x86_tests(void)
static void add_s390x_tests(void)
{
if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) {
g_test_skip("No KVM or TCG accelerator available, skipping boot tests");
return;
}
qtest_add_data_func("cdrom/boot/default", "-cdrom ", test_cdboot);
qtest_add_data_func("cdrom/boot/virtio-scsi",
"-device virtio-scsi -device scsi-cd,drive=cdr "

4
ui/console.c
View File

@ -311,7 +311,7 @@ static bool png_save(int fd, pixman_image_t *image, Error **errp)
png_struct *png_ptr;
png_info *info_ptr;
g_autoptr(pixman_image_t) linebuf =
qemu_pixman_linebuf_create(PIXMAN_a8r8g8b8, width);
qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width);
uint8_t *buf = (uint8_t *)pixman_image_get_data(linebuf);
FILE *f = fdopen(fd, "wb");
int y;
@ -341,7 +341,7 @@ static bool png_save(int fd, pixman_image_t *image, Error **errp)
png_init_io(png_ptr, f);
png_set_IHDR(png_ptr, info_ptr, width, height, 8,
PNG_COLOR_TYPE_RGB_ALPHA, PNG_INTERLACE_NONE,
PNG_COLOR_TYPE_RGB, PNG_INTERLACE_NONE,
PNG_COMPRESSION_TYPE_BASE, PNG_FILTER_TYPE_BASE);
png_write_info(png_ptr, info_ptr);