target/arm: Handle FEAT_NV page table attribute changes
FEAT_NV requires that when HCR_EL2.{NV,NV1} == {1,1} the handling of some of the page table attribute bits changes for the EL1&0 translation regime: * for block and page descriptors: - bit [54] holds PXN, not UXN - bit [53] is RES0, and the effective value of UXN is 0 - bit [6], AP[1], is treated as 0 * for table descriptors, when hierarchical permissions are enabled: - bit [60] holds PXNTable, not UXNTable - bit [59] is RES0 - bit [61], APTable[0] is treated as 0 Implement these changes to the page table attribute handling. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Miguel Luis <miguel.luis@oracle.com>
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@ -1581,6 +1581,12 @@ static bool lpae_block_desc_valid(ARMCPU *cpu, bool ds,
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}
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static bool nv_nv1_enabled(CPUARMState *env, S1Translate *ptw)
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{
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uint64_t hcr = arm_hcr_el2_eff_secstate(env, ptw->in_space);
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return (hcr & (HCR_NV | HCR_NV1)) == (HCR_NV | HCR_NV1);
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}
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/**
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* get_phys_addr_lpae: perform one stage of page table walk, LPAE format
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*
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@ -1989,6 +1995,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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xn = extract64(attrs, 54, 1);
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pxn = extract64(attrs, 53, 1);
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if (el == 1 && nv_nv1_enabled(env, ptw)) {
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/*
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* With FEAT_NV, when HCR_EL2.{NV,NV1} == {1,1}, the block/page
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* descriptor bit 54 holds PXN, 53 is RES0, and the effective value
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* of UXN is 0. Similarly for bits 59 and 60 in table descriptors
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* (which we have already folded into bits 53 and 54 of attrs).
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* AP[1] (descriptor bit 6, our ap bit 0) is treated as 0.
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* Similarly, APTable[0] from the table descriptor is treated as 0;
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* we already folded this into AP[1] and squashing that to 0 does
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* the right thing.
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*/
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pxn = xn;
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xn = 0;
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ap &= ~1;
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}
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/*
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* Note that we modified ptw->in_space earlier for NSTable, but
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* result->f.attrs retains a copy of the original security space.
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