target/xtensa: add DFPU option
Double precision floating point unit is a FPU implementation different from the FPU2000 in the following ways: - it may be configured with only single or with both single and double precision operations support; - it may be configured with division and square root opcodes; - FSR register accumulates inValid, division by Zero, Overflow, Underflow and Inexact result flags of operations; - QNaNs and SNaNs are handled properly; - NaN propagation rules are different. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
parent
5dbb4c96d5
commit
de6b55cbda
@ -52,6 +52,8 @@ enum {
|
|||||||
XTENSA_OPTION_COPROCESSOR,
|
XTENSA_OPTION_COPROCESSOR,
|
||||||
XTENSA_OPTION_BOOLEAN,
|
XTENSA_OPTION_BOOLEAN,
|
||||||
XTENSA_OPTION_FP_COPROCESSOR,
|
XTENSA_OPTION_FP_COPROCESSOR,
|
||||||
|
XTENSA_OPTION_DFP_COPROCESSOR,
|
||||||
|
XTENSA_OPTION_DFPU_SINGLE_ONLY,
|
||||||
XTENSA_OPTION_MP_SYNCHRO,
|
XTENSA_OPTION_MP_SYNCHRO,
|
||||||
XTENSA_OPTION_CONDITIONAL_STORE,
|
XTENSA_OPTION_CONDITIONAL_STORE,
|
||||||
XTENSA_OPTION_ATOMCTL,
|
XTENSA_OPTION_ATOMCTL,
|
||||||
|
@ -39,6 +39,26 @@
|
|||||||
#define XCHAL_HAVE_DEPBITS 0
|
#define XCHAL_HAVE_DEPBITS 0
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifndef XCHAL_HAVE_DFP
|
||||||
|
#define XCHAL_HAVE_DFP 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef XCHAL_HAVE_DFPU_SINGLE_ONLY
|
||||||
|
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef XCHAL_HAVE_DFPU_SINGLE_DOUBLE
|
||||||
|
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE XCHAL_HAVE_DFP
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We need to know the type of FP unit, not only its precision.
|
||||||
|
* Unfortunately XCHAL macros don't tell this explicitly.
|
||||||
|
*/
|
||||||
|
#define XCHAL_HAVE_DFPU (XCHAL_HAVE_DFP || \
|
||||||
|
XCHAL_HAVE_DFPU_SINGLE_ONLY || \
|
||||||
|
XCHAL_HAVE_DFPU_SINGLE_DOUBLE)
|
||||||
|
|
||||||
#ifndef XCHAL_HAVE_DIV32
|
#ifndef XCHAL_HAVE_DIV32
|
||||||
#define XCHAL_HAVE_DIV32 0
|
#define XCHAL_HAVE_DIV32 0
|
||||||
#endif
|
#endif
|
||||||
@ -99,6 +119,9 @@
|
|||||||
XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
|
XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
|
||||||
XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
|
XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
|
||||||
XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
|
XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
|
||||||
|
XCHAL_OPTION(XCHAL_HAVE_DFPU, XTENSA_OPTION_DFP_COPROCESSOR) | \
|
||||||
|
XCHAL_OPTION(XCHAL_HAVE_DFPU_SINGLE_ONLY, \
|
||||||
|
XTENSA_OPTION_DFPU_SINGLE_ONLY) | \
|
||||||
XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
|
XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
|
||||||
XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
|
XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
|
||||||
XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
|
XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
|
||||||
|
Loading…
Reference in New Issue
Block a user