tcg-aarch64: Implement TCG_TARGET_HAS_new_ldst
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
Richard Henderson
parent
667b1cdd4e
commit
de61d14fa7
@ -1047,21 +1047,27 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
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/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
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* int mmu_idx, uintptr_t ra)
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*/
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static const void * const qemu_ld_helpers[4] = {
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helper_ret_ldub_mmu,
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helper_ret_lduw_mmu,
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helper_ret_ldul_mmu,
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helper_ret_ldq_mmu,
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static const void * const qemu_ld_helpers[16] = {
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[MO_UB] = helper_ret_ldub_mmu,
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[MO_LEUW] = helper_le_lduw_mmu,
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[MO_LEUL] = helper_le_ldul_mmu,
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[MO_LEQ] = helper_le_ldq_mmu,
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[MO_BEUW] = helper_be_lduw_mmu,
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[MO_BEUL] = helper_be_ldul_mmu,
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[MO_BEQ] = helper_be_ldq_mmu,
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};
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/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
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* uintxx_t val, int mmu_idx, uintptr_t ra)
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*/
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static const void * const qemu_st_helpers[4] = {
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helper_ret_stb_mmu,
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helper_ret_stw_mmu,
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helper_ret_stl_mmu,
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helper_ret_stq_mmu,
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static const void * const qemu_st_helpers[16] = {
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[MO_UB] = helper_ret_stb_mmu,
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[MO_LEUW] = helper_le_stw_mmu,
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[MO_LEUL] = helper_le_stl_mmu,
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[MO_LEQ] = helper_le_stq_mmu,
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[MO_BEUW] = helper_be_stw_mmu,
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[MO_BEUL] = helper_be_stl_mmu,
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[MO_BEQ] = helper_be_stq_mmu,
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};
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static inline void tcg_out_adr(TCGContext *s, TCGReg rd, uintptr_t addr)
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@ -1082,7 +1088,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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tcg_out_movr(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index);
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tcg_out_adr(s, TCG_REG_X3, (intptr_t)lb->raddr);
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tcg_out_call(s, (intptr_t)qemu_ld_helpers[size]);
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tcg_out_call(s, (intptr_t)qemu_ld_helpers[opc & ~MO_SIGN]);
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if (opc & MO_SIGN) {
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tcg_out_sxt(s, TCG_TYPE_I64, size, lb->datalo_reg, TCG_REG_X0);
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} else {
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@ -1094,7 +1100,8 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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TCGMemOp size = lb->opc;
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TCGMemOp opc = lb->opc;
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TCGMemOp size = opc & MO_SIZE;
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reloc_pc19(lb->label_ptr[0], (intptr_t)s->code_ptr);
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@ -1103,7 +1110,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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tcg_out_movr(s, size == MO_64, TCG_REG_X2, lb->datalo_reg);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index);
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tcg_out_adr(s, TCG_REG_X4, (intptr_t)lb->raddr);
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tcg_out_call(s, (intptr_t)qemu_st_helpers[size]);
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tcg_out_call(s, (intptr_t)qemu_st_helpers[opc]);
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tcg_out_goto(s, (intptr_t)lb->raddr);
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}
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@ -1572,39 +1579,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]);
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break;
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case INDEX_op_qemu_ld8u:
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tcg_out_qemu_ld(s, a0, a1, MO_UB, a2);
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case INDEX_op_qemu_ld_i32:
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case INDEX_op_qemu_ld_i64:
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tcg_out_qemu_ld(s, a0, a1, a2, args[3]);
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break;
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case INDEX_op_qemu_ld8s:
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tcg_out_qemu_ld(s, a0, a1, MO_SB, a2);
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break;
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case INDEX_op_qemu_ld16u:
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tcg_out_qemu_ld(s, a0, a1, MO_TEUW, a2);
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break;
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case INDEX_op_qemu_ld16s:
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tcg_out_qemu_ld(s, a0, a1, MO_TESW, a2);
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break;
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case INDEX_op_qemu_ld32u:
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case INDEX_op_qemu_ld32:
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tcg_out_qemu_ld(s, a0, a1, MO_TEUL, a2);
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break;
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case INDEX_op_qemu_ld32s:
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tcg_out_qemu_ld(s, a0, a1, MO_TESL, a2);
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break;
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case INDEX_op_qemu_ld64:
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tcg_out_qemu_ld(s, a0, a1, MO_TEQ, a2);
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break;
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case INDEX_op_qemu_st8:
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tcg_out_qemu_st(s, a0, a1, MO_UB, a2);
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break;
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case INDEX_op_qemu_st16:
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tcg_out_qemu_st(s, a0, a1, MO_TEUW, a2);
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break;
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case INDEX_op_qemu_st32:
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tcg_out_qemu_st(s, a0, a1, MO_TEUL, a2);
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break;
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case INDEX_op_qemu_st64:
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tcg_out_qemu_st(s, a0, a1, MO_TEQ, a2);
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case INDEX_op_qemu_st_i32:
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case INDEX_op_qemu_st_i64:
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tcg_out_qemu_st(s, a0, a1, a2, args[3]);
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break;
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case INDEX_op_bswap32_i64:
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@ -1770,20 +1751,10 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
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{ INDEX_op_movcond_i32, { "r", "r", "rwA", "rZ", "rZ" } },
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{ INDEX_op_movcond_i64, { "r", "r", "rA", "rZ", "rZ" } },
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{ INDEX_op_qemu_ld8u, { "r", "l" } },
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{ INDEX_op_qemu_ld8s, { "r", "l" } },
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{ INDEX_op_qemu_ld16u, { "r", "l" } },
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{ INDEX_op_qemu_ld16s, { "r", "l" } },
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{ INDEX_op_qemu_ld32u, { "r", "l" } },
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{ INDEX_op_qemu_ld32s, { "r", "l" } },
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{ INDEX_op_qemu_ld32, { "r", "l" } },
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{ INDEX_op_qemu_ld64, { "r", "l" } },
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{ INDEX_op_qemu_st8, { "l", "l" } },
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{ INDEX_op_qemu_st16, { "l", "l" } },
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{ INDEX_op_qemu_st32, { "l", "l" } },
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{ INDEX_op_qemu_st64, { "l", "l" } },
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{ INDEX_op_qemu_ld_i32, { "r", "l" } },
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{ INDEX_op_qemu_ld_i64, { "r", "l" } },
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{ INDEX_op_qemu_st_i32, { "l", "l" } },
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{ INDEX_op_qemu_st_i64, { "l", "l" } },
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{ INDEX_op_bswap16_i32, { "r", "r" } },
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{ INDEX_op_bswap32_i32, { "r", "r" } },
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@ -98,7 +98,7 @@ typedef enum {
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#define TCG_TARGET_HAS_muluh_i64 1
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#define TCG_TARGET_HAS_mulsh_i64 1
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#define TCG_TARGET_HAS_new_ldst 0
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#define TCG_TARGET_HAS_new_ldst 1
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static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
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{
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