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target/mips: Have gen_addiupc() expand $pc during translation

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Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241010215015.44326-12-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-10-10 16:46:26 -03:00
parent 2803e24694
commit de0029664f
1 changed files with 4 additions and 6 deletions
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10
target/mips/tcg/translate.c
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@ -11428,20 +11428,18 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
void gen_addiupc(DisasContext *ctx, int rx, int imm, void gen_addiupc(DisasContext *ctx, int rx, int imm,
int is_64_bit, int extended) int is_64_bit, int extended)
{ {
TCGv t0; target_ulong npc;
if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
return; return;
} }
t0 = tcg_temp_new(); npc = pc_relative_pc(ctx) + imm;
tcg_gen_movi_tl(t0, pc_relative_pc(ctx));
tcg_gen_addi_tl(cpu_gpr[rx], t0, imm);
if (!is_64_bit) { if (!is_64_bit) {
tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); npc = (int32_t)npc;
} }
tcg_gen_movi_tl(cpu_gpr[rx], npc);
} }
static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,