target-arm: Infer ARMv4T feature from ARMv5
V5 => V4T Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
dd4ebc2ecd
commit
ddb572ec48
@ -53,7 +53,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
env->cp15.c0_cpuid = id;
|
||||
switch (id) {
|
||||
case ARM_CPUID_ARM926:
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_VFP);
|
||||
env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
|
||||
@ -61,14 +60,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
env->cp15.c1_sys = 0x00090078;
|
||||
break;
|
||||
case ARM_CPUID_ARM946:
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_MPU);
|
||||
env->cp15.c0_cachetype = 0x0f004006;
|
||||
env->cp15.c1_sys = 0x00000078;
|
||||
break;
|
||||
case ARM_CPUID_ARM1026:
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_VFP);
|
||||
set_feature(env, ARM_FEATURE_AUXCR);
|
||||
@ -85,7 +82,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
* older core than plain "arm1136". In particular this does not
|
||||
* have the v6K features.
|
||||
*/
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_V6);
|
||||
set_feature(env, ARM_FEATURE_VFP);
|
||||
@ -103,7 +99,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
env->cp15.c1_sys = 0x00050078;
|
||||
break;
|
||||
case ARM_CPUID_ARM1176:
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_V6);
|
||||
set_feature(env, ARM_FEATURE_V6K);
|
||||
@ -119,7 +114,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
env->cp15.c1_sys = 0x00050078;
|
||||
break;
|
||||
case ARM_CPUID_ARM11MPCORE:
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_V6);
|
||||
set_feature(env, ARM_FEATURE_V6K);
|
||||
@ -134,7 +128,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
env->cp15.c0_cachetype = 0x1dd20d2;
|
||||
break;
|
||||
case ARM_CPUID_CORTEXA8:
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_V6);
|
||||
set_feature(env, ARM_FEATURE_V6K);
|
||||
@ -158,7 +151,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
env->cp15.c1_sys = 0x00c50078;
|
||||
break;
|
||||
case ARM_CPUID_CORTEXA9:
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_V6);
|
||||
set_feature(env, ARM_FEATURE_V6K);
|
||||
@ -187,7 +179,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
env->cp15.c1_sys = 0x00c50078;
|
||||
break;
|
||||
case ARM_CPUID_CORTEXM3:
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_V6);
|
||||
set_feature(env, ARM_FEATURE_THUMB2);
|
||||
@ -196,7 +187,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
set_feature(env, ARM_FEATURE_THUMB_DIV);
|
||||
break;
|
||||
case ARM_CPUID_ANY: /* For userspace emulation. */
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_V6);
|
||||
set_feature(env, ARM_FEATURE_V6K);
|
||||
@ -226,7 +216,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
case ARM_CPUID_PXA260:
|
||||
case ARM_CPUID_PXA261:
|
||||
case ARM_CPUID_PXA262:
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_XSCALE);
|
||||
/* JTAG_ID is ((id << 28) | 0x09265013) */
|
||||
@ -239,7 +228,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
case ARM_CPUID_PXA270_B1:
|
||||
case ARM_CPUID_PXA270_C0:
|
||||
case ARM_CPUID_PXA270_C5:
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_XSCALE);
|
||||
/* JTAG_ID is ((id << 28) | 0x09265013) */
|
||||
@ -262,6 +250,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
if (arm_feature(env, ARM_FEATURE_V7)) {
|
||||
set_feature(env, ARM_FEATURE_VAPA);
|
||||
}
|
||||
if (arm_feature(env, ARM_FEATURE_V5)) {
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
}
|
||||
if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
|
||||
set_feature(env, ARM_FEATURE_THUMB_DIV);
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user