target-ppc: remove PRECISE_EMULATION define
The PRECISE_EMULATION is "hardcoded" to one in target-ppc/exec.h and not something easily tunable. Remove it and non-precise emulation code as it doesn't make a noticeable difference in speed. People wanting speed improvement should use softfloat-native instead. Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Aurelien Jarno
parent
23979dc541
commit
dd94ad96e5
@ -26,9 +26,6 @@
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#include "cpu.h"
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#include "exec-all.h"
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/* Precise emulation is needed to correctly emulate exception flags */
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#define USE_PRECISE_EMULATION 1
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register struct CPUPPCState *env asm(AREG0);
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#if !defined(CONFIG_USER_ONLY)
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@ -974,7 +974,7 @@ uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
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farg1.ll = arg1;
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farg2.ll = arg2;
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#if USE_PRECISE_EMULATION
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if (unlikely(float64_is_signaling_nan(farg1.d) ||
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float64_is_signaling_nan(farg2.d))) {
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/* sNaN addition */
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@ -986,9 +986,7 @@ uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
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} else {
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farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
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}
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#else
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farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
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#endif
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return farg1.ll;
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}
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@ -999,8 +997,7 @@ uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
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farg1.ll = arg1;
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farg2.ll = arg2;
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#if USE_PRECISE_EMULATION
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{
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if (unlikely(float64_is_signaling_nan(farg1.d) ||
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float64_is_signaling_nan(farg2.d))) {
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/* sNaN subtraction */
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@ -1012,10 +1009,7 @@ uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
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} else {
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farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
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}
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}
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#else
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farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
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#endif
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return farg1.ll;
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}
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@ -1026,7 +1020,7 @@ uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
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farg1.ll = arg1;
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farg2.ll = arg2;
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#if USE_PRECISE_EMULATION
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if (unlikely(float64_is_signaling_nan(farg1.d) ||
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float64_is_signaling_nan(farg2.d))) {
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/* sNaN multiplication */
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@ -1038,9 +1032,7 @@ uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
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} else {
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farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
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}
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#else
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farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
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#endif
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return farg1.ll;
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}
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@ -1051,7 +1043,7 @@ uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
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farg1.ll = arg1;
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farg2.ll = arg2;
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#if USE_PRECISE_EMULATION
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if (unlikely(float64_is_signaling_nan(farg1.d) ||
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float64_is_signaling_nan(farg2.d))) {
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/* sNaN division */
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@ -1065,9 +1057,7 @@ uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
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} else {
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farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
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}
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#else
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farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
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#endif
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return farg1.ll;
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}
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@ -1116,12 +1106,10 @@ uint64_t helper_fctiw (uint64_t arg)
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farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
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} else {
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farg.ll = float64_to_int32(farg.d, &env->fp_status);
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#if USE_PRECISE_EMULATION
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/* XXX: higher bits are not supposed to be significant.
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* to make tests easier, return the same as a real PowerPC 750
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*/
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farg.ll |= 0xFFF80000ULL << 32;
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#endif
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}
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return farg.ll;
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}
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@ -1140,12 +1128,10 @@ uint64_t helper_fctiwz (uint64_t arg)
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farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
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} else {
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farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
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#if USE_PRECISE_EMULATION
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/* XXX: higher bits are not supposed to be significant.
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* to make tests easier, return the same as a real PowerPC 750
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*/
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farg.ll |= 0xFFF80000ULL << 32;
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#endif
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}
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return farg.ll;
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}
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@ -1245,7 +1231,7 @@ uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
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farg1.ll = arg1;
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farg2.ll = arg2;
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farg3.ll = arg3;
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#if USE_PRECISE_EMULATION
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if (unlikely(float64_is_signaling_nan(farg1.d) ||
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float64_is_signaling_nan(farg2.d) ||
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float64_is_signaling_nan(farg3.d))) {
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@ -1277,10 +1263,7 @@ uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
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farg1.d = (farg1.d * farg2.d) + farg3.d;
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#endif
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}
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#else
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farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
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farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
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#endif
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return farg1.ll;
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}
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@ -1292,7 +1275,7 @@ uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
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farg1.ll = arg1;
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farg2.ll = arg2;
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farg3.ll = arg3;
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#if USE_PRECISE_EMULATION
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if (unlikely(float64_is_signaling_nan(farg1.d) ||
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float64_is_signaling_nan(farg2.d) ||
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float64_is_signaling_nan(farg3.d))) {
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@ -1324,10 +1307,6 @@ uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
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farg1.d = (farg1.d * farg2.d) - farg3.d;
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#endif
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}
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#else
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farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
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farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
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#endif
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return farg1.ll;
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}
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@ -1350,7 +1329,6 @@ uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
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/* Multiplication of zero by infinity */
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farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
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} else {
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#if USE_PRECISE_EMULATION
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#ifdef FLOAT128
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/* This is the way the PowerPC specification defines it */
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float128 ft0_128, ft1_128;
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@ -1370,10 +1348,6 @@ uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
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#else
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/* This is OK on x86 hosts */
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farg1.d = (farg1.d * farg2.d) + farg3.d;
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#endif
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#else
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farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
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farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
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#endif
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if (likely(!float64_is_quiet_nan(farg1.d)))
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farg1.d = float64_chs(farg1.d);
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@ -1400,7 +1374,6 @@ uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
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/* Multiplication of zero by infinity */
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farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
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} else {
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#if USE_PRECISE_EMULATION
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#ifdef FLOAT128
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/* This is the way the PowerPC specification defines it */
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float128 ft0_128, ft1_128;
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@ -1420,10 +1393,6 @@ uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
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#else
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/* This is OK on x86 hosts */
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farg1.d = (farg1.d * farg2.d) - farg3.d;
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#endif
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#else
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farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
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farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
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#endif
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if (likely(!float64_is_quiet_nan(farg1.d)))
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farg1.d = float64_chs(farg1.d);
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@ -1438,7 +1407,6 @@ uint64_t helper_frsp (uint64_t arg)
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float32 f32;
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farg.ll = arg;
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#if USE_PRECISE_EMULATION
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if (unlikely(float64_is_signaling_nan(farg.d))) {
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/* sNaN square root */
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farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
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@ -1446,10 +1414,6 @@ uint64_t helper_frsp (uint64_t arg)
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f32 = float64_to_float32(farg.d, &env->fp_status);
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farg.d = float32_to_float64(f32, &env->fp_status);
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}
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#else
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f32 = float64_to_float32(farg.d, &env->fp_status);
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farg.d = float32_to_float64(f32, &env->fp_status);
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#endif
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return farg.ll;
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}
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