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target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

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We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.

Fixes: d6f20dacea ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-2-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2022-02-04 23:16:37 +05:30 committed by Alistair Francis
parent ac6bcf4d46
commit dceecac8a2
1 changed files with 1 additions and 1 deletions
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2
target/riscv/csr.c
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@ -186,7 +186,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
static RISCVException hmode32(CPURISCVState *env, int csrno) static RISCVException hmode32(CPURISCVState *env, int csrno)
{ {
if (riscv_cpu_mxl(env) != MXL_RV32) { if (riscv_cpu_mxl(env) != MXL_RV32) {
if (riscv_cpu_virt_enabled(env)) { if (!riscv_cpu_virt_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST; return RISCV_EXCP_ILLEGAL_INST;
} else { } else {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;