target/mips: Set correct CP0.Config[4, 5] values for M14K(c)
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230216051717.3911212-5-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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@ -332,7 +332,10 @@ const mips_def_t mips_defs[] =
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(0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1,
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
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.CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt) |
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(1 << CP0C3_M),
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.CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
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.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
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.CP0_Config7 = 1 << CP0C7_WII,
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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@ -354,7 +357,10 @@ const mips_def_t mips_defs[] =
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
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.CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt) |
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(1 << CP0C3_M),
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.CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
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.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
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.CP0_Config7 = 1 << CP0C7_WII,
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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