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Misc HW patch queue

Browse Source 
hw: Remove sysbus_address_space() (Phil)
 hw/nubus: Add nubus-virtio-mmio device (Mark)
 hw/usb: Remove usb_bus_find() (Paolo)
 hw/usb: Extract sysbus-ohci from ohci (Paolo)
 hw/nvme: Fix invalid endian conversion
 hw/i386: More PC machine housekeeping (Bernhard, Phil)
 hw/ide: Restrict "ide-internal.h" (Zoltan, Phil)
 qom: Expose object_resolve_type_unambiguous() (Paolo)
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Merge tag 'hw-misc-20240227' of https://github.com/philmd/qemu into staging

Misc HW patch queue

hw: Remove sysbus_address_space() (Phil)
hw/nubus: Add nubus-virtio-mmio device (Mark)
hw/usb: Remove usb_bus_find() (Paolo)
hw/usb: Extract sysbus-ohci from ohci (Paolo)
hw/nvme: Fix invalid endian conversion
hw/i386: More PC machine housekeeping (Bernhard, Phil)
hw/ide: Restrict "ide-internal.h" (Zoltan, Phil)
qom: Expose object_resolve_type_unambiguous() (Paolo)

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# gpg: Signature made Tue 27 Feb 2024 08:38:11 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-misc-20240227' of https://github.com/philmd/qemu: (30 commits)
  hw/ide: Include 'ide-internal.h' from current path
  hw/ide: Remove last two uses of ide/internal.h outside of hw/ide/
  hw/arm/sbsa-ref: Do not open-code ahci_ide_create_devs()
  hw/i386/pc: Populate RTC attribute directly
  hw/i386/pc: Remove unneeded class attribute "kvmclock_enabled"
  hw/i386/pc_{piix, q35}: Eliminate local pci_bus/pci_host variables
  hw/i386/pc: Rename "bus" attribute to "pcibus"
  hw/i386/q35: Include missing 'hw/acpi/acpi.h' header
  hw/i386/sgx: Use QDev API
  hw/i386/x86: Let ioapic_init_gsi() take parent as pointer
  hw/nvme: fix invalid endian conversion
  hw/usb: remove duplicate file in system_ss
  hw/usb: extract sysbus-ohci to a separate file
  hw/usb: remove usb_bus_find
  hw/ppc/pseries: do not require CONFIG_USB
  hw/ppc/mac_newworld: do not require CONFIG_USB
  hw/hppa: do not require CONFIG_USB
  hw/mips/loongson3_virt: do not require CONFIG_USB
  hw/sh4/r2d: do not use usb_bus_find()
  hw/ppc/sam460ex: do not use usb_bus_find()
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-02-27 10:11:07 +00:00
commit dccbaf0cc0
67 changed files with 473 additions and 242 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
hw/arm/Kconfig
View File

@ -185,7 +185,7 @@ config PXA2XX
select SERIAL
select SD
select SSI
select USB_OHCI
select USB_OHCI_SYSBUS
select PCMCIA
config GUMSTIX
@ -256,7 +256,7 @@ config REALVIEW
select PL310 # cache controller
select ARM_SBCON_I2C
select DS1338 # I2C RTC+NVRAM
select USB_OHCI
select USB_OHCI_SYSBUS
config SBSA_REF
bool
@ -339,7 +339,7 @@ config VERSATILE
select PL080 # DMA controller
select PL190 # Vector PIC
select REALVIEW
select USB_OHCI
select USB_OHCI_SYSBUS
config VEXPRESS
bool
@ -395,6 +395,7 @@ config ALLWINNER_A10
select AXP2XX_PMU
select SERIAL
select UNIMP
select USB_OHCI_SYSBUS
config ALLWINNER_H3
bool
@ -408,7 +409,7 @@ config ALLWINNER_H3
select ARM_TIMER
select ARM_GIC
select UNIMP
select USB_OHCI
select USB_OHCI_SYSBUS
select USB_EHCI_SYSBUS
select SD
@ -424,7 +425,7 @@ config ALLWINNER_R40
select ARM_TIMER
select ARM_GIC
select UNIMP
select USB_OHCI
select USB_OHCI_SYSBUS
select USB_EHCI_SYSBUS
select SD
@ -530,6 +531,7 @@ config NPCM7XX
select SSI
select UNIMP
select PCA954X
select USB_OHCI_SYSBUS
config FSL_IMX25
bool

14
hw/arm/exynos4210.c
View File

@ -769,11 +769,15 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
}
/*** Display controller (FIMD) ***/
sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
s->irq_table[exynos4210_get_irq(11, 0)],
s->irq_table[exynos4210_get_irq(11, 1)],
s->irq_table[exynos4210_get_irq(11, 2)],
NULL);
dev = qdev_new("exynos4210.fimd");
object_property_set_link(OBJECT(dev), "framebuffer-memory",
OBJECT(system_mem), &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_FIMD0_BASE_ADDR);
for (n = 0; n < 3; n++) {
sysbus_connect_irq(busdev, n, s->irq_table[exynos4210_get_irq(11, n)]);
}
sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
s->irq_table[exynos4210_get_irq(28, 3)]);

7
hw/arm/integratorcp.c
View File

@ -670,7 +670,12 @@ static void integratorcp_init(MachineState *machine)
smc91c111_init(0xc8000000, pic[27]);
}
sysbus_create_simple("pl110", 0xc0000000, pic[22]);
dev = qdev_new("pl110");
object_property_set_link(OBJECT(dev), "framebuffer-memory",
OBJECT(address_space_mem), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xc0000000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[22]);
integrator_binfo.ram_size = ram_size;
arm_load_kernel(cpu, machine, &integrator_binfo);

7
hw/arm/realview.c
View File

@ -238,7 +238,12 @@ static void realview_init(MachineState *machine,
sysbus_create_simple("pl061", 0x10014000, pic[7]);
gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
sysbus_create_simple("pl111", 0x10020000, pic[23]);
dev = qdev_new("pl111");
object_property_set_link(OBJECT(dev), "framebuffer-memory",
OBJECT(sysmem), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10020000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[23]);
dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
/* Wire up MMC card detect and read-only signals. These have

13
hw/arm/sbsa-ref.c
View File

@ -36,8 +36,7 @@
#include "hw/arm/smmuv3.h"
#include "hw/block/flash.h"
#include "hw/boards.h"
#include "hw/ide/internal.h"
#include "hw/ide/ahci_internal.h"
#include "hw/ide/ide-bus.h"
#include "hw/ide/ahci-sysbus.h"
#include "hw/intc/arm_gicv3_common.h"
#include "hw/intc/arm_gicv3_its_common.h"
@ -571,8 +570,6 @@ static void create_ahci(const SBSAMachineState *sms)
DeviceState *dev;
DriveInfo *hd[NUM_SATA_PORTS];
SysbusAHCIState *sysahci;
AHCIState *ahci;
int i;
dev = qdev_new("sysbus-ahci");
qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
@ -581,14 +578,8 @@ static void create_ahci(const SBSAMachineState *sms)
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
sysahci = SYSBUS_AHCI(dev);
ahci = &sysahci->ahci;
ide_drive_get(hd, ARRAY_SIZE(hd));
for (i = 0; i < ahci->ports; i++) {
if (hd[i] == NULL) {
continue;
}
ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]);
}
ahci_ide_create_devs(&sysahci->ahci, hd);
}
static void create_xhci(const SBSAMachineState *sms)

8
hw/arm/versatilepb.c
View File

@ -299,7 +299,13 @@ static void versatile_init(MachineState *machine, int board_id)
/* The versatile/PB actually has a modified Color LCD controller
that includes hardware cursor support from the PL111. */
dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
dev = qdev_new("pl110_versatile");
object_property_set_link(OBJECT(dev), "framebuffer-memory",
OBJECT(sysmem), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10120000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[16]);
/* Wire up the mux control signals from the SYS_CLCD register */
qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));

15
hw/arm/vexpress.c
View File

@ -276,6 +276,7 @@ static void a9_daughterboard_init(VexpressMachineState *vms,
{
MachineState *machine = MACHINE(vms);
MemoryRegion *sysmem = get_system_memory();
DeviceState *dev;
if (ram_size > 0x40000000) {
/* 1GB is the maximum the address space permits */
@ -297,7 +298,12 @@ static void a9_daughterboard_init(VexpressMachineState *vms,
/* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
/* 0x10020000 PL111 CLCD (daughterboard) */
sysbus_create_simple("pl111", 0x10020000, pic[44]);
dev = qdev_new("pl111");
object_property_set_link(OBJECT(dev), "framebuffer-memory",
OBJECT(sysmem), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10020000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[44]);
/* 0x10060000 AXI RAM */
/* 0x100e0000 PL341 Dynamic Memory Controller */
@ -650,7 +656,12 @@ static void vexpress_common_init(MachineState *machine)
/* VE_COMPACTFLASH: not modelled */
sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
dev = qdev_new("pl111");
object_property_set_link(OBJECT(dev), "framebuffer-memory",
OBJECT(sysmem), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, map[VE_CLCD]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[14]);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",

5
hw/core/sysbus.c
View File

@ -298,11 +298,6 @@ static char *sysbus_get_fw_dev_path(DeviceState *dev)
return g_strdup(qdev_fw_name(dev));
}
MemoryRegion *sysbus_address_space(SysBusDevice *dev)
{
return get_system_memory();
}
static void sysbus_device_class_init(ObjectClass *klass, void *data)
{
DeviceClass *k = DEVICE_CLASS(klass);

1
hw/display/Kconfig
View File

@ -77,6 +77,7 @@ config SM501
select I2C
select DDC
select SERIAL
select USB_OHCI_SYSBUS
config TCX
bool

19
hw/display/exynos4210_fimd.c
View File

@ -23,6 +23,7 @@
*/
#include "qemu/osdep.h"
#include "hw/qdev-properties.h"
#include "hw/hw.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
@ -32,6 +33,7 @@
#include "qemu/bswap.h"
#include "qemu/module.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "qom/object.h"
/* Debug messages configuration */
@ -302,6 +304,7 @@ struct Exynos4210fimdState {
MemoryRegion iomem;
QemuConsole *console;
qemu_irq irq[3];
MemoryRegion *fbmem;
uint32_t vidcon[4]; /* Video main control registers 0-3 */
uint32_t vidtcon[4]; /* Video time control registers 0-3 */
@ -1119,7 +1122,6 @@ static void exynos4210_fimd_invalidate(void *opaque)
* VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */
static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
Exynos4210fimdWindow *w = &s->window[win];
hwaddr fb_start_addr, fb_mapped_len;
@ -1147,8 +1149,7 @@ static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
memory_region_unref(w->mem_section.mr);
}
w->mem_section = memory_region_find(sysbus_address_space(sbd),
fb_start_addr, w->fb_len);
w->mem_section = memory_region_find(s->fbmem, fb_start_addr, w->fb_len);
assert(w->mem_section.mr);
assert(w->mem_section.offset_within_address_space == fb_start_addr);
DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n",
@ -1924,6 +1925,12 @@ static const GraphicHwOps exynos4210_fimd_ops = {
.gfx_update = exynos4210_fimd_update,
};
static Property exynos4210_fimd_properties[] = {
DEFINE_PROP_LINK("framebuffer-memory", Exynos4210fimdState, fbmem,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
static void exynos4210_fimd_init(Object *obj)
{
Exynos4210fimdState *s = EXYNOS4210_FIMD(obj);
@ -1944,6 +1951,11 @@ static void exynos4210_fimd_realize(DeviceState *dev, Error **errp)
{
Exynos4210fimdState *s = EXYNOS4210_FIMD(dev);
if (!s->fbmem) {
error_setg(errp, "'framebuffer-memory' property was not set");
return;
}
s->console = graphic_console_init(dev, 0, &exynos4210_fimd_ops, s);
}
@ -1954,6 +1966,7 @@ static void exynos4210_fimd_class_init(ObjectClass *klass, void *data)
dc->vmsd = &exynos4210_fimd_vmstate;
dc->reset = exynos4210_fimd_reset;
dc->realize = exynos4210_fimd_realize;
device_class_set_props(dc, exynos4210_fimd_properties);
}
static const TypeInfo exynos4210_fimd_info = {

20
hw/display/pl110.c
View File

@ -10,6 +10,7 @@
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "ui/console.h"
#include "framebuffer.h"
@ -17,6 +18,7 @@
#include "qemu/timer.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qapi/error.h"
#include "qom/object.h"
#define PL110_CR_EN 0x001
@ -74,6 +76,7 @@ struct PL110State {
uint32_t palette[256];
uint32_t raw_palette[128];
qemu_irq irq;
MemoryRegion *fbmem;
};
static int vmstate_pl110_post_load(void *opaque, int version_id);
@ -210,7 +213,6 @@ static int pl110_enabled(PL110State *s)
static void pl110_update_display(void *opaque)
{
PL110State *s = (PL110State *)opaque;
SysBusDevice *sbd;
DisplaySurface *surface = qemu_console_surface(s->con);
drawfn fn;
int src_width;
@ -222,8 +224,6 @@ static void pl110_update_display(void *opaque)
return;
}
sbd = SYS_BUS_DEVICE(s);
if (s->cr & PL110_CR_BGR)
bpp_offset = 0;
else
@ -290,7 +290,7 @@ static void pl110_update_display(void *opaque)
first = 0;
if (s->invalidate) {
framebuffer_update_memory_section(&s->fbsection,
sysbus_address_space(sbd),
s->fbmem,
s->upbase,
s->rows, src_width);
}
@ -535,11 +535,22 @@ static const GraphicHwOps pl110_gfx_ops = {
.gfx_update = pl110_update_display,
};
static Property pl110_properties[] = {
DEFINE_PROP_LINK("framebuffer-memory", PL110State, fbmem,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
static void pl110_realize(DeviceState *dev, Error **errp)
{
PL110State *s = PL110(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
if (!s->fbmem) {
error_setg(errp, "'framebuffer-memory' property was not set");
return;
}
memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
@ -577,6 +588,7 @@ static void pl110_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->vmsd = &vmstate_pl110;
dc->realize = pl110_realize;
device_class_set_props(dc, pl110_properties);
}
static const TypeInfo pl110_info = {

2
hw/hppa/Kconfig
View File

@ -2,6 +2,7 @@ config HPPA_B160L
bool
imply PCI_DEVICES
imply E1000_PCI
imply USB_OHCI_PCI
imply VIRTIO_VGA
select ASTRO
select DINO
@ -17,4 +18,3 @@ config HPPA_B160L
select LASIPS2
select PARALLEL
select ARTIST
select USB_OHCI_PCI

10
hw/hppa/machine.c
View File

@ -396,10 +396,14 @@ static void machine_HP_common_init_tail(MachineState *machine, PCIBus *pci_bus,
}
/* create USB OHCI controller for USB keyboard & mouse on Astro machines */
if (!lasi_dev && machine->enable_graphics) {
if (!lasi_dev && machine->enable_graphics && defaults_enabled()) {
USBBus *usb_bus;
pci_create_simple(pci_bus, -1, "pci-ohci");
usb_create_simple(usb_bus_find(-1), "usb-kbd");
usb_create_simple(usb_bus_find(-1), "usb-mouse");
usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS,
&error_abort));
usb_create_simple(usb_bus, "usb-kbd");
usb_create_simple(usb_bus, "usb-mouse");
}
/* register power switch emulation */

22
hw/i386/acpi-build.c
View File

@ -192,21 +192,10 @@ static void init_common_fadt_data(MachineState *ms, Object *o,
*data = fadt;
}
static Object *object_resolve_type_unambiguous(const char *typename)
{
bool ambig;
Object *o = object_resolve_path_type("", typename, &ambig);
if (ambig || !o) {
return NULL;
}
return o;
}
static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
{
Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL);
Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL);
Object *obj = piix ? piix : lpc;
QObject *o;
pm->cpu_hp_io_base = 0;
@ -1428,8 +1417,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
AcpiPmInfo *pm, AcpiMiscInfo *misc,
Range *pci_hole, Range *pci_hole64, MachineState *machine)
{
Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE);
Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE);
Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE,
NULL);
Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL);
CrsRangeEntry *entry;
Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
CrsRangeSet crs_range_set;
@ -1556,7 +1546,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
}
crs_range_set_init(&crs_range_set);
bus = PC_MACHINE(machine)->bus;
bus = PC_MACHINE(machine)->pcibus;
if (bus) {
QLIST_FOREACH(bus, &bus->child, sibling) {
uint8_t bus_num = pci_bus_num(bus);

2
hw/i386/amd_iommu.c
View File

@ -1584,7 +1584,7 @@ static void amdvi_sysbus_realize(DeviceState *dev, Error **errp)
MachineState *ms = MACHINE(qdev_get_machine());
PCMachineState *pcms = PC_MACHINE(ms);
X86MachineState *x86ms = X86_MACHINE(ms);
PCIBus *bus = pcms->bus;
PCIBus *bus = pcms->pcibus;
s->iotlb = g_hash_table_new_full(amdvi_uint64_hash,
amdvi_uint64_equal, g_free, g_free);

2
hw/i386/intel_iommu.c
View File

@ -4183,7 +4183,7 @@ static void vtd_realize(DeviceState *dev, Error **errp)
MachineState *ms = MACHINE(qdev_get_machine());
PCMachineState *pcms = PC_MACHINE(ms);
X86MachineState *x86ms = X86_MACHINE(ms);
PCIBus *bus = pcms->bus;
PCIBus *bus = pcms->pcibus;
IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);

2
hw/i386/kvm/xen_evtchn.c
View File

@ -371,7 +371,7 @@ static int set_callback_pci_intx(XenEvtchnState *s, uint64_t param)
return 0;
}
pdev = pci_find_device(pcms->bus, bus, devfn);
pdev = pci_find_device(pcms->pcibus, bus, devfn);
if (!pdev) {
return 0;
}

11
hw/i386/kvmvapic.c
View File

@ -58,6 +58,7 @@ typedef struct GuestROMState {
struct VAPICROMState {
SysBusDevice busdev;
MemoryRegion io;
MemoryRegion rom;
uint32_t state;
@ -581,19 +582,17 @@ static int vapic_map_rom_writable(VAPICROMState *s)
{
hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
MemoryRegionSection section;
MemoryRegion *as;
MemoryRegion *mr = get_system_memory();
size_t rom_size;
uint8_t *ram;
as = sysbus_address_space(&s->busdev);
if (s->rom_mapped_writable) {
memory_region_del_subregion(as, &s->rom);
memory_region_del_subregion(mr, &s->rom);
object_unparent(OBJECT(&s->rom));
}
/* grab RAM memory region (region @rom_paddr may still be pc.rom) */
section = memory_region_find(as, 0, 1);
section = memory_region_find(mr, 0, 1);
/* read ROM size from RAM region */
if (rom_paddr + 2 >= memory_region_size(section.mr)) {
@ -614,7 +613,7 @@ static int vapic_map_rom_writable(VAPICROMState *s)
memory_region_init_alias(&s->rom, OBJECT(s), "kvmvapic-rom", section.mr,
rom_paddr, rom_size);
memory_region_add_subregion_overlap(as, rom_paddr, &s->rom, 1000);
memory_region_add_subregion_overlap(mr, rom_paddr, &s->rom, 1000);
s->rom_mapped_writable = true;
memory_region_unref(section.mr);

2
hw/i386/microvm.c
View File

@ -175,7 +175,7 @@ static void microvm_devices_init(MicrovmMachineState *mms)
&error_abort);
isa_bus_register_input_irqs(isa_bus, x86ms->gsi);
ioapic_init_gsi(gsi_state, "machine");
ioapic_init_gsi(gsi_state, OBJECT(mms));
if (ioapics > 1) {
x86ms->ioapic2 = ioapic_init_secondary(gsi_state);
}

17
hw/i386/pc.c
View File

@ -611,14 +611,6 @@ void pc_cmos_init(PCMachineState *pcms,
mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
object_property_add_link(OBJECT(pcms), "rtc_state",
TYPE_ISA_DEVICE,
(Object **)&x86ms->rtc,
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG);
object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
&error_abort);
set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
val = 0;
@ -675,7 +667,7 @@ void pc_machine_done(Notifier *notifier, void *data)
PCMachineState, machine_done);
X86MachineState *x86ms = X86_MACHINE(pcms);
cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state,
&error_fatal);
if (pcms->cxl_devices_state.is_enabled) {
@ -685,7 +677,7 @@ void pc_machine_done(Notifier *notifier, void *data)
/* set the number of CPUs */
x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg);
acpi_setup();
if (x86ms->fw_cfg) {
@ -1250,8 +1242,8 @@ void pc_basic_device_init(struct PCMachineState *pcms,
xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
xen_gnttab_create();
xen_xenstore_create();
if (pcms->bus) {
pci_create_simple(pcms->bus, -1, "xen-platform");
if (pcms->pcibus) {
pci_create_simple(pcms->pcibus, -1, "xen-platform");
}
xen_bus_init();
xen_be_init();
@ -1799,7 +1791,6 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
pcmc->smbios_uuid_encoded = true;
pcmc->gigabyte_align = true;
pcmc->has_reserved_memory = true;
pcmc->kvmclock_enabled = true;
pcmc->enforce_aligned_dimm = true;
pcmc->enforce_amd_1tb_hole = true;
/* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported

42
hw/i386/pc_piix.c
View File

@ -107,12 +107,11 @@ static void pc_init1(MachineState *machine,
X86MachineState *x86ms = X86_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
PCIBus *pci_bus = NULL;
Object *phb = NULL;
ISABus *isa_bus;
Object *piix4_pm = NULL;
qemu_irq smi_irq;
GSIState *gsi_state;
ISADevice *rtc_state;
MemoryRegion *ram_memory;
MemoryRegion *pci_memory = NULL;
MemoryRegion *rom_memory = system_memory;
@ -184,13 +183,11 @@ static void pc_init1(MachineState *machine,
pc_machine_init_sgx_epc(pcms);
x86_cpus_init(x86ms, pcmc->default_cpu_version);
if (kvm_enabled() && pcmc->kvmclock_enabled) {
if (kvm_enabled()) {
kvmclock_create(pcmc->kvmclock_create_always);
}
if (pcmc->pci_enabled) {
Object *phb;
pci_memory = g_new(MemoryRegion, 1);
memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
rom_memory = pci_memory;
@ -213,11 +210,10 @@ static void pc_init1(MachineState *machine,
&error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal);
pci_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0"));
pci_bus_map_irqs(pci_bus,
pcms->pcibus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0"));
pci_bus_map_irqs(pcms->pcibus,
xen_enabled() ? xen_pci_slot_get_pirq
: pc_pci_slot_get_pirq);
pcms->bus = pci_bus;
hole64_size = object_property_get_uint(phb,
PCI_HOST_PROP_PCI_HOLE64_SIZE,
@ -262,7 +258,7 @@ static void pc_init1(MachineState *machine,
for (i = 0; i < ISA_NUM_IRQS; i++) {
qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]);
}
pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
pci_realize_and_unref(pci_dev, pcms->pcibus, &error_fatal);
if (xen_enabled()) {
pci_device_set_intx_routing_notifier(
@ -274,13 +270,13 @@ static void pc_init1(MachineState *machine,
* connected to the IOAPIC directly.
* These additional routes can be discovered through ACPI.
*/
pci_bus_irqs(pci_bus, xen_intx_set_irq, pci_dev,
pci_bus_irqs(pcms->pcibus, xen_intx_set_irq, pci_dev,
XEN_IOAPIC_NUM_PIRQS);
}
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
"rtc"));
x86ms->rtc = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
"rtc"));
piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm");
dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide"));
pci_ide_create_devs(PCI_DEVICE(dev));
@ -291,9 +287,9 @@ static void pc_init1(MachineState *machine,
&error_abort);
isa_bus_register_input_irqs(isa_bus, x86ms->gsi);
rtc_state = isa_new(TYPE_MC146818_RTC);
qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000);
isa_realize_and_unref(rtc_state, isa_bus, &error_fatal);
x86ms->rtc = isa_new(TYPE_MC146818_RTC);
qdev_prop_set_int32(DEVICE(x86ms->rtc), "base_year", 2000);
isa_realize_and_unref(x86ms->rtc, isa_bus, &error_fatal);
i8257_dma_init(OBJECT(machine), isa_bus, 0);
pcms->hpet_enabled = false;
@ -303,15 +299,15 @@ static void pc_init1(MachineState *machine,
pc_i8259_create(isa_bus, gsi_state->i8259_irq);
}
if (pcmc->pci_enabled) {
ioapic_init_gsi(gsi_state, "i440fx");
if (phb) {
ioapic_init_gsi(gsi_state, phb);
}
if (tcg_enabled()) {
x86_register_ferr_irq(x86ms->gsi[13]);
}
pc_vga_init(isa_bus, pcmc->pci_enabled ? pci_bus : NULL);
pc_vga_init(isa_bus, pcmc->pci_enabled ? pcms->pcibus : NULL);
assert(pcms->vmport != ON_OFF_AUTO__MAX);
if (pcms->vmport == ON_OFF_AUTO_AUTO) {
@ -319,10 +315,10 @@ static void pc_init1(MachineState *machine,
}
/* init basic PC hardware */
pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, true,
pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, true,
0x4);
pc_nic_init(pcmc, isa_bus, pci_bus);
pc_nic_init(pcmc, isa_bus, pcms->pcibus);
#ifdef CONFIG_IDE_ISA
if (!pcmc->pci_enabled) {
@ -346,7 +342,7 @@ static void pc_init1(MachineState *machine,
}
#endif
pc_cmos_init(pcms, rtc_state);
pc_cmos_init(pcms, x86ms->rtc);
if (piix4_pm) {
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
@ -481,8 +477,8 @@ static void pc_xen_hvm_init(MachineState *machine)
}
pc_xen_hvm_init_pci(machine);
xen_igd_reserve_slot(pcms->bus);
pci_create_simple(pcms->bus, -1, "xen-platform");
xen_igd_reserve_slot(pcms->pcibus);
pci_create_simple(pcms->pcibus, -1, "xen-platform");
}
#endif

26
hw/i386/pc_q35.c
View File

@ -30,6 +30,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/acpi/acpi.h"
#include "hw/char/parallel-isa.h"
#include "hw/loader.h"
#include "hw/i2c/smbus_eeprom.h"
@ -122,10 +123,8 @@ static void pc_q35_init(MachineState *machine)
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
X86MachineState *x86ms = X86_MACHINE(machine);
Object *phb;
PCIBus *host_bus;
PCIDevice *lpc;
DeviceState *lpc_dev;
ISADevice *rtc_state;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
MemoryRegion *pci_memory = g_new(MemoryRegion, 1);
@ -216,8 +215,7 @@ static void pc_q35_init(MachineState *machine)
sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal);
/* pci */
host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0"));
pcms->bus = host_bus;
pcms->pcibus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0"));
/* irq lines */
gsi_state = pc_gsi_create(&x86ms->gsi, true);
@ -231,9 +229,9 @@ static void pc_q35_init(MachineState *machine)
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
pci_realize_and_unref(lpc, host_bus, &error_fatal);
pci_realize_and_unref(lpc, pcms->pcibus, &error_fatal);
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc"));
x86ms->rtc = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc"));
object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
TYPE_HOTPLUG_HANDLER,
@ -263,7 +261,7 @@ static void pc_q35_init(MachineState *machine)
pc_i8259_create(isa_bus, gsi_state->i8259_irq);
}
ioapic_init_gsi(gsi_state, "q35");
ioapic_init_gsi(gsi_state, OBJECT(phb));
if (tcg_enabled()) {
x86_register_ferr_irq(x86ms->gsi[13]);
@ -275,7 +273,7 @@ static void pc_q35_init(MachineState *machine)
}
/* init basic PC hardware */
pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy,
pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, !mc->no_floppy,
0xff0104);
if (pcms->sata_enabled) {
@ -283,7 +281,7 @@ static void pc_q35_init(MachineState *machine)
AHCIPCIState *ich9;
/* ahci and SATA device, for q35 1 ahci controller is built-in */
pdev = pci_create_simple_multifunction(host_bus,
pdev = pci_create_simple_multifunction(pcms->pcibus,
PCI_DEVFN(ICH9_SATA1_DEV,
ICH9_SATA1_FUNC),
"ich9-ahci");
@ -297,14 +295,14 @@ static void pc_q35_init(MachineState *machine)
if (machine_usb(machine)) {
/* Should we create 6 UHCI according to ich9 spec? */
ehci_create_ich9_with_companions(host_bus, 0x1d);
ehci_create_ich9_with_companions(pcms->pcibus, 0x1d);
}
if (pcms->smbus_enabled) {
PCIDevice *smb;
/* TODO: Populate SPD eeprom data. */
smb = pci_create_simple_multifunction(host_bus,
smb = pci_create_simple_multifunction(pcms->pcibus,
PCI_DEVFN(ICH9_SMB_DEV,
ICH9_SMB_FUNC),
TYPE_ICH9_SMB_DEVICE);
@ -313,11 +311,11 @@ static void pc_q35_init(MachineState *machine)
smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
}
pc_cmos_init(pcms, rtc_state);
pc_cmos_init(pcms, x86ms->rtc);
/* the rest devices to which pci devfn is automatically assigned */
pc_vga_init(isa_bus, host_bus);
pc_nic_init(pcmc, isa_bus, host_bus);
pc_vga_init(isa_bus, pcms->pcibus);
pc_nic_init(pcmc, isa_bus, pcms->pcibus);
if (machine->nvdimms_state->is_enabled) {
nvdimm_init_acpi_state(machine->nvdimms_state, system_io,

14
hw/i386/sgx.c
View File

@ -286,7 +286,6 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms)
SGXEPCState *sgx_epc = &pcms->sgx_epc;
X86MachineState *x86ms = X86_MACHINE(pcms);
SgxEPCList *list = NULL;
Object *obj;
memset(sgx_epc, 0, sizeof(SGXEPCState));
if (!x86ms->sgx_epc_list) {
@ -300,16 +299,15 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms)
&sgx_epc->mr);
for (list = x86ms->sgx_epc_list; list; list = list->next) {
obj = object_new("sgx-epc");
DeviceState *dev = qdev_new(TYPE_SGX_EPC);
/* set the memdev link with memory backend */
object_property_parse(obj, SGX_EPC_MEMDEV_PROP, list->value->memdev,
&error_fatal);
object_property_parse(OBJECT(dev), SGX_EPC_MEMDEV_PROP,
list->value->memdev, &error_fatal);
/* set the numa node property for sgx epc object */
object_property_set_uint(obj, SGX_EPC_NUMA_NODE_PROP, list->value->node,
&error_fatal);
object_property_set_bool(obj, "realized", true, &error_fatal);
object_unref(obj);
object_property_set_uint(OBJECT(dev), SGX_EPC_NUMA_NODE_PROP,
list->value->node, &error_fatal);
qdev_realize_and_unref(dev, NULL, &error_fatal);
}
if ((sgx_epc->base + sgx_epc->size) < sgx_epc->base) {

2
hw/i386/x86-iommu.c
View File

@ -101,7 +101,7 @@ static void x86_iommu_realize(DeviceState *dev, Error **errp)
QLIST_INIT(&x86_iommu->iec_notifiers);
bool irq_all_kernel = kvm_irqchip_in_kernel() && !kvm_irqchip_is_split();
if (!pcms || !pcms->bus) {
if (!pcms || !pcms->pcibus) {
error_setg(errp, "Machine-type '%s' not supported by IOMMU",
mc->name);
return;

7
hw/i386/x86.c
View File

@ -640,20 +640,19 @@ void gsi_handler(void *opaque, int n, int level)
}
}
void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
void ioapic_init_gsi(GSIState *gsi_state, Object *parent)
{
DeviceState *dev;
SysBusDevice *d;
unsigned int i;
assert(parent_name);
assert(parent);
if (kvm_ioapic_in_kernel()) {
dev = qdev_new(TYPE_KVM_IOAPIC);
} else {
dev = qdev_new(TYPE_IOAPIC);
}
object_property_add_child(object_resolve_path(parent_name, NULL),
"ioapic", OBJECT(dev));
object_property_add_child(parent, "ioapic", OBJECT(dev));
d = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(d, &error_fatal);
sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);

2
hw/ide/ahci.c
View File

@ -34,11 +34,11 @@
#include "qemu/module.h"
#include "sysemu/block-backend.h"
#include "sysemu/dma.h"
#include "hw/ide/internal.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci-pci.h"
#include "hw/ide/ahci-sysbus.h"
#include "ahci_internal.h"
#include "ide-internal.h"
#include "trace.h"

2
hw/ide/ahci_internal.h
View File

@ -25,8 +25,8 @@
#define HW_IDE_AHCI_INTERNAL_H
#include "hw/ide/ahci.h"
#include "hw/ide/internal.h"
#include "hw/pci/pci_device.h"
#include "ide-internal.h"
#define AHCI_MEM_BAR_SIZE 0x1000
#define AHCI_MAX_PORTS 32

2
hw/ide/atapi.c
View File

@ -24,10 +24,10 @@
*/
#include "qemu/osdep.h"
#include "hw/ide/internal.h"
#include "hw/scsi/scsi.h"
#include "sysemu/block-backend.h"
#include "scsi/constants.h"
#include "ide-internal.h"
#include "trace.h"
#define ATAPI_SECTOR_BITS (2 + BDRV_SECTOR_BITS)

2
hw/ide/cmd646.c
View File

@ -33,7 +33,7 @@
#include "sysemu/reset.h"
#include "hw/ide/pci.h"
#include "hw/ide/internal.h"
#include "ide-internal.h"
#include "trace.h"
/* CMD646 specific */

2
hw/ide/core.c
View File

@ -41,7 +41,7 @@
#include "qemu/cutils.h"
#include "sysemu/replay.h"
#include "sysemu/runstate.h"
#include "hw/ide/internal.h"
#include "ide-internal.h"
#include "trace.h"
/* These values were based on a Seagate ST3500418AS but have been modified

2
hw/ide/ide-bus.c
View File

@ -21,10 +21,10 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "hw/ide/internal.h"
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "sysemu/runstate.h"
#include "ide-internal.h"
static char *idebus_get_fw_dev_path(DeviceState *dev);
static void idebus_unrealize(BusState *qdev);

2
hw/ide/ide-dev.c
View File

@ -23,11 +23,11 @@
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "hw/ide/ide-dev.h"
#include "hw/ide/internal.h"
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "sysemu/sysemu.h"
#include "qapi/visitor.h"
#include "ide-internal.h"
static Property ide_props[] = {
DEFINE_PROP_UINT32("unit", IDEDevice, unit, -1),

0
include/hw/ide/internal.h → hw/ide/ide-internal.h
View File

2
hw/ide/ioport.c
View File

@ -25,7 +25,7 @@
#include "qemu/osdep.h"
#include "hw/isa/isa.h"
#include "hw/ide/internal.h"
#include "ide-internal.h"
#include "trace.h"
int ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)

2
hw/ide/isa.c
View File

@ -32,8 +32,8 @@
#include "sysemu/dma.h"
#include "hw/ide/isa.h"
#include "hw/ide/internal.h"
#include "qom/object.h"
#include "ide-internal.h"
/***********************************************************/
/* ISA IDE definitions */

2
hw/ide/macio.c
View File

@ -33,7 +33,7 @@
#include "sysemu/block-backend.h"
#include "sysemu/dma.h"
#include "hw/ide/internal.h"
#include "ide-internal.h"
/* debug MACIO */
// #define DEBUG_MACIO

2
hw/ide/microdrive.c
View File

@ -31,8 +31,8 @@
#include "sysemu/dma.h"
#include "hw/irq.h"
#include "hw/ide/internal.h"
#include "qom/object.h"
#include "ide-internal.h"
#define TYPE_MICRODRIVE "microdrive"
OBJECT_DECLARE_SIMPLE_TYPE(MicroDriveState, MICRODRIVE)

2
hw/ide/mmio.c
View File

@ -30,8 +30,8 @@
#include "sysemu/dma.h"
#include "hw/ide/mmio.h"
#include "hw/ide/internal.h"
#include "hw/qdev-properties.h"
#include "ide-internal.h"
/***********************************************************/
/* MMIO based ide port

2
hw/ide/pci.c
View File

@ -30,8 +30,8 @@
#include "sysemu/dma.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "hw/ide/internal.h"
#include "hw/ide/pci.h"
#include "ide-internal.h"
#include "trace.h"
#define BMDMA_PAGE_SIZE 4096

2
hw/ide/piix.c
View File

@ -30,9 +30,9 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/pci/pci.h"
#include "hw/ide/internal.h"
#include "hw/ide/piix.h"
#include "hw/ide/pci.h"
#include "ide-internal.h"
#include "trace.h"
static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)

2
hw/ide/sii3112.c
View File

@ -13,11 +13,11 @@
*/
#include "qemu/osdep.h"
#include "hw/ide/internal.h"
#include "hw/ide/pci.h"
#include "qemu/module.h"
#include "trace.h"
#include "qom/object.h"
#include "ide-internal.h"
#define TYPE_SII3112_PCI "sii3112"
OBJECT_DECLARE_SIMPLE_TYPE(SiI3112PCIState, SII3112_PCI)

2
hw/ide/via.c
View File

@ -25,7 +25,6 @@
*/
#include "qemu/osdep.h"
#include "hw/ide/internal.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
@ -34,6 +33,7 @@
#include "hw/isa/vt82c686.h"
#include "hw/ide/pci.h"
#include "hw/irq.h"
#include "ide-internal.h"
#include "trace.h"
static uint64_t bmdma_read(void *opaque, hwaddr addr,

8
hw/mips/loongson3_virt.c
View File

@ -446,9 +446,13 @@ static inline void loongson3_virt_devices_init(MachineState *machine,
pci_vga_init(pci_bus);
if (defaults_enabled() && object_class_by_name("pci-ohci")) {
USBBus *usb_bus;
pci_create_simple(pci_bus, -1, "pci-ohci");
usb_create_simple(usb_bus_find(-1), "usb-kbd");
usb_create_simple(usb_bus_find(-1), "usb-tablet");
usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS,
&error_abort));
usb_create_simple(usb_bus, "usb-kbd");
usb_create_simple(usb_bus, "usb-tablet");
}
pci_init_nic_devices(pci_bus, mc->default_nic);

1
hw/nubus/meson.build
View File

@ -2,6 +2,7 @@ nubus_ss = ss.source_set()
nubus_ss.add(files('nubus-device.c'))
nubus_ss.add(files('nubus-bus.c'))
nubus_ss.add(files('nubus-bridge.c'))
nubus_ss.add(files('nubus-virtio-mmio.c'))
nubus_ss.add(when: 'CONFIG_Q800', if_true: files('mac-nubus-bridge.c'))
system_ss.add_all(when: 'CONFIG_NUBUS', if_true: nubus_ss)

18
hw/nubus/nubus-device.c
View File

@ -10,6 +10,7 @@
#include "qemu/osdep.h"
#include "qemu/datadir.h"
#include "exec/target_page.h"
#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/nubus/nubus.h"
@ -30,7 +31,8 @@ static void nubus_device_realize(DeviceState *dev, Error **errp)
NubusDevice *nd = NUBUS_DEVICE(dev);
char *name, *path;
hwaddr slot_offset;
int64_t size;
int64_t size, align_size;
uint8_t *rom_ptr;
int ret;
/* Super */
@ -76,16 +78,24 @@ static void nubus_device_realize(DeviceState *dev, Error **errp)
}
name = g_strdup_printf("nubus-slot-%x-declaration-rom", nd->slot);
memory_region_init_rom(&nd->decl_rom, OBJECT(dev), name, size,
/*
* Ensure ROM memory region is aligned to target page size regardless
* of the size of the Declaration ROM image
*/
align_size = ROUND_UP(size, qemu_target_page_size());
memory_region_init_rom(&nd->decl_rom, OBJECT(dev), name, align_size,
&error_abort);
ret = load_image_mr(path, &nd->decl_rom);
rom_ptr = memory_region_get_ram_ptr(&nd->decl_rom);
ret = load_image_size(path, rom_ptr + (uintptr_t)(align_size - size),
size);
g_free(path);
g_free(name);
if (ret < 0) {
error_setg(errp, "could not load romfile \"%s\"", nd->romfile);
return;
}
memory_region_add_subregion(&nd->slot_mem, NUBUS_SLOT_SIZE - size,
memory_region_add_subregion(&nd->slot_mem, NUBUS_SLOT_SIZE - align_size,
&nd->decl_rom);
}
}

102
hw/nubus/nubus-virtio-mmio.c Normal file
View File

@ -0,0 +1,102 @@
/*
* QEMU Macintosh Nubus Virtio MMIO card
*
* Copyright (c) 2024 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "hw/nubus/nubus-virtio-mmio.h"
#define NUBUS_VIRTIO_MMIO_PIC_OFFSET 0
#define NUBUS_VIRTIO_MMIO_DEV_OFFSET 0x200
static void nubus_virtio_mmio_set_input_irq(void *opaque, int n, int level)
{
NubusDevice *nd = NUBUS_DEVICE(opaque);
nubus_set_irq(nd, level);
}
static void nubus_virtio_mmio_realize(DeviceState *dev, Error **errp)
{
NubusVirtioMMIODeviceClass *nvmdc = NUBUS_VIRTIO_MMIO_GET_CLASS(dev);
NubusVirtioMMIO *s = NUBUS_VIRTIO_MMIO(dev);
NubusDevice *nd = NUBUS_DEVICE(dev);
SysBusDevice *sbd;
int i, offset;
nvmdc->parent_realize(dev, errp);
if (*errp) {
return;
}
/* Goldfish PIC */
sbd = SYS_BUS_DEVICE(&s->pic);
if (!sysbus_realize(sbd, errp)) {
return;
}
memory_region_add_subregion(&nd->slot_mem, NUBUS_VIRTIO_MMIO_PIC_OFFSET,
sysbus_mmio_get_region(sbd, 0));
sysbus_connect_irq(sbd, 0,
qdev_get_gpio_in_named(dev, "pic-input-irq", 0));
/* virtio-mmio devices */
offset = NUBUS_VIRTIO_MMIO_DEV_OFFSET;
for (i = 0; i < NUBUS_VIRTIO_MMIO_NUM_DEVICES; i++) {
sbd = SYS_BUS_DEVICE(&s->virtio_mmio[i]);
qdev_prop_set_bit(DEVICE(sbd), "force-legacy", false);
if (!sysbus_realize_and_unref(sbd, errp)) {
return;
}
memory_region_add_subregion(&nd->slot_mem, offset,
sysbus_mmio_get_region(sbd, 0));
offset += 0x200;
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(&s->pic), i));
}
}
static void nubus_virtio_mmio_init(Object *obj)
{
NubusVirtioMMIO *s = NUBUS_VIRTIO_MMIO(obj);
int i;
object_initialize_child(obj, "pic", &s->pic, TYPE_GOLDFISH_PIC);
for (i = 0; i < NUBUS_VIRTIO_MMIO_NUM_DEVICES; i++) {
char *name = g_strdup_printf("virtio-mmio[%d]", i);
object_initialize_child(obj, name, &s->virtio_mmio[i],
TYPE_VIRTIO_MMIO);
g_free(name);
}
/* Input from goldfish PIC */
qdev_init_gpio_in_named(DEVICE(obj), nubus_virtio_mmio_set_input_irq,
"pic-input-irq", 1);
}
static void nubus_virtio_mmio_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
NubusVirtioMMIODeviceClass *nvmdc = NUBUS_VIRTIO_MMIO_CLASS(oc);
device_class_set_parent_realize(dc, nubus_virtio_mmio_realize,
&nvmdc->parent_realize);
}
static const TypeInfo nubus_virtio_mmio_types[] = {
{
.name = TYPE_NUBUS_VIRTIO_MMIO,
.parent = TYPE_NUBUS_DEVICE,
.instance_init = nubus_virtio_mmio_init,
.instance_size = sizeof(NubusVirtioMMIO),
.class_init = nubus_virtio_mmio_class_init,
.class_size = sizeof(NubusVirtioMMIODeviceClass),
},
};
DEFINE_TYPES(nubus_virtio_mmio_types)

2
hw/nvme/ctrl.c
View File

@ -7924,7 +7924,7 @@ static void nvme_init_state(NvmeCtrl *n)
n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1);
QTAILQ_INIT(&n->aer_queue);
list->numcntl = cpu_to_le16(max_vfs);
list->numcntl = max_vfs;
for (i = 0; i < max_vfs; i++) {
sctrl = &list->sec[i];
sctrl->pcid = cpu_to_le16(n->cntlid);

5
hw/ppc/Kconfig
View File

@ -1,5 +1,6 @@
config PSERIES
bool
imply USB_OHCI_PCI
imply PCI_DEVICES
imply TEST_DEVICES
imply VIRTIO_VGA
@ -69,7 +70,7 @@ config SAM460EX
select SM501
select SMBUS_EEPROM
select USB_EHCI_SYSBUS
select USB_OHCI
select USB_OHCI_SYSBUS
select FDT_PPC
config AMIGAONE
@ -119,13 +120,13 @@ config MAC_NEWWORLD
imply PCI_DEVICES
imply SUNGEM
imply TEST_DEVICES
imply USB_OHCI_PCI
select ADB
select MACIO
select MACIO_GPIO
select MAC_PMU
select UNIN_PCI
select FW_CFG_PPC
select USB_OHCI_PCI
config E500
bool

4
hw/ppc/mac_newworld.c
View File

@ -431,8 +431,10 @@ static void ppc_core99_init(MachineState *machine)
/* U3 needs to use USB for input because Linux doesn't support via-cuda
on PPC64 */
if (!has_adb || machine_arch == ARCH_MAC99_U3) {
USBBus *usb_bus = usb_bus_find(-1);
USBBus *usb_bus;
usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS,
&error_abort));
usb_create_simple(usb_bus, "usb-kbd");
usb_create_simple(usb_bus, "usb-mouse");
}

7
hw/ppc/sam460ex.c
View File

@ -274,6 +274,7 @@ static void sam460ex_init(MachineState *machine)
DeviceState *uic[4];
int i;
PCIBus *pci_bus;
USBBus *usb_bus;
PowerPCCPU *cpu;
CPUPPCState *env;
I2CBus *i2c;
@ -421,8 +422,10 @@ static void sam460ex_init(MachineState *machine)
sysbus_realize_and_unref(sbdev, &error_fatal);
sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30));
usb_create_simple(usb_bus_find(-1), "usb-kbd");
usb_create_simple(usb_bus_find(-1), "usb-mouse");
usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS,
&error_abort));
usb_create_simple(usb_bus, "usb-kbd");
usb_create_simple(usb_bus, "usb-mouse");
/* PCIe buses */
dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);

4
hw/ppc/spapr.c
View File

@ -3024,8 +3024,10 @@ static void spapr_machine_init(MachineState *machine)
}
if (has_vga) {
USBBus *usb_bus = usb_bus_find(-1);
USBBus *usb_bus;
usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS,
&error_abort));
usb_create_simple(usb_bus, "usb-kbd");
usb_create_simple(usb_bus, "usb-mouse");
}

1
hw/sh4/Kconfig
View File

@ -6,7 +6,6 @@ config R2D
select I82378 if TEST_DEVICES
select IDE_MMIO
select PFLASH_CFI02
select USB_OHCI_PCI
select PCI
select SM501
select SH7750

5
hw/sh4/r2d.c
View File

@ -244,6 +244,7 @@ static void r2d_init(MachineState *machine)
SysBusDevice *busdev;
MemoryRegion *address_space_mem = get_system_memory();
PCIBus *pci_bus;
USBBus *usb_bus;
cpu = SUPERH_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
@ -312,7 +313,9 @@ static void r2d_init(MachineState *machine)
pci_init_nic_devices(pci_bus, mc->default_nic);
/* USB keyboard */
usb_create_simple(usb_bus_find(-1), "usb-kbd");
usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS,
&error_abort));
usb_create_simple(usb_bus, "usb-kbd");
/* Todo: register on board registers */
memset(&boot_params, 0, sizeof(boot_params));

4
hw/usb/Kconfig
View File

@ -11,6 +11,10 @@ config USB_OHCI
bool
select USB
config USB_OHCI_SYSBUS
bool
select USB_OHCI
config USB_OHCI_PCI
bool
default y if PCI_DEVICES

15
hw/usb/bus.c
View File

@ -100,19 +100,6 @@ void usb_bus_release(USBBus *bus)
QTAILQ_REMOVE(&busses, bus, next);
}
USBBus *usb_bus_find(int busnr)
{
USBBus *bus;
if (-1 == busnr)
return QTAILQ_FIRST(&busses);
QTAILQ_FOREACH(bus, &busses, next) {
if (bus->busnr == busnr)
return bus;
}
return NULL;
}
static void usb_device_realize(USBDevice *dev, Error **errp)
{
USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
@ -643,7 +630,7 @@ HumanReadableText *qmp_x_query_usb(Error **errp)
/* handle legacy -usbdevice cmd line option */
USBDevice *usbdevice_create(const char *driver)
{
USBBus *bus = usb_bus_find(-1 /* any */);
USBBus *bus = QTAILQ_FIRST(&busses);
LegacyUSBFactory *f = NULL;
Error *err = NULL;
GSList *i;

88
hw/usb/hcd-ohci-sysbus.c Normal file
View File

@ -0,0 +1,88 @@
/*
* QEMU USB OHCI Emulation
* Copyright (c) 2006 Openedhand Ltd.
* Copyright (c) 2010 CodeSourcery
* Copyright (c) 2024 Red Hat, Inc.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "hw/usb.h"
#include "migration/vmstate.h"
#include "hw/sysbus.h"
#include "hw/qdev-dma.h"
#include "hw/qdev-properties.h"
#include "trace.h"
#include "hcd-ohci.h"
static void ohci_sysbus_realize(DeviceState *dev, Error **errp)
{
OHCISysBusState *s = SYSBUS_OHCI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Error *err = NULL;
usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset,
s->masterbus, s->firstport,
&address_space_memory, ohci_sysbus_die, &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_init_irq(sbd, &s->ohci.irq);
sysbus_init_mmio(sbd, &s->ohci.mem);
}
static void ohci_sysbus_reset(DeviceState *dev)
{
OHCISysBusState *s = SYSBUS_OHCI(dev);
OHCIState *ohci = &s->ohci;
ohci_hard_reset(ohci);
}
static Property ohci_sysbus_properties[] = {
DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus),
DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0),
DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ohci_sysbus_realize;
set_bit(DEVICE_CATEGORY_USB, dc->categories);
dc->desc = "OHCI USB Controller";
device_class_set_props(dc, ohci_sysbus_properties);
dc->reset = ohci_sysbus_reset;
}
static const TypeInfo ohci_sysbus_types[] = {
{
.name = TYPE_SYSBUS_OHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(OHCISysBusState),
.class_init = ohci_sysbus_class_init,
},
};
DEFINE_TYPES(ohci_sysbus_types);

58
hw/usb/hcd-ohci.c
View File

@ -1955,31 +1955,6 @@ void ohci_sysbus_die(struct OHCIState *ohci)
ohci_bus_stop(ohci);
}
static void ohci_realize_pxa(DeviceState *dev, Error **errp)
{
OHCISysBusState *s = SYSBUS_OHCI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Error *err = NULL;
usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset,
s->masterbus, s->firstport,
&address_space_memory, ohci_sysbus_die, &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_init_irq(sbd, &s->ohci.irq);
sysbus_init_mmio(sbd, &s->ohci.mem);
}
static void usb_ohci_reset_sysbus(DeviceState *dev)
{
OHCISysBusState *s = SYSBUS_OHCI(dev);
OHCIState *ohci = &s->ohci;
ohci_hard_reset(ohci);
}
static const VMStateDescription vmstate_ohci_state_port = {
.name = "ohci-core/port",
.version_id = 1,
@ -2054,36 +2029,3 @@ const VMStateDescription vmstate_ohci_state = {
NULL
}
};
static Property ohci_sysbus_properties[] = {
DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus),
DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0),
DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ohci_realize_pxa;
set_bit(DEVICE_CATEGORY_USB, dc->categories);
dc->desc = "OHCI USB Controller";
device_class_set_props(dc, ohci_sysbus_properties);
dc->reset = usb_ohci_reset_sysbus;
}
static const TypeInfo ohci_sysbus_info = {
.name = TYPE_SYSBUS_OHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(OHCISysBusState),
.class_init = ohci_sysbus_class_init,
};
static void ohci_register_types(void)
{
type_register_static(&ohci_sysbus_info);
}
type_init(ohci_register_types)

3
hw/usb/meson.build
View File

@ -15,9 +15,10 @@ system_ss.add(when: 'CONFIG_USB', if_true: files(
system_ss.add(when: 'CONFIG_USB_UHCI', if_true: files('hcd-uhci.c'))
system_ss.add(when: 'CONFIG_USB_OHCI', if_true: files('hcd-ohci.c'))
system_ss.add(when: 'CONFIG_USB_OHCI_PCI', if_true: files('hcd-ohci-pci.c'))
system_ss.add(when: 'CONFIG_USB_OHCI_SYSBUS', if_true: files('hcd-ohci-sysbus.c'))
system_ss.add(when: 'CONFIG_USB_EHCI', if_true: files('hcd-ehci.c'))
system_ss.add(when: 'CONFIG_USB_EHCI_PCI', if_true: files('hcd-ehci-pci.c'))
system_ss.add(when: 'CONFIG_USB_EHCI_SYSBUS', if_true: files('hcd-ehci.c', 'hcd-ehci-sysbus.c'))
system_ss.add(when: 'CONFIG_USB_EHCI_SYSBUS', if_true: files('hcd-ehci-sysbus.c'))
system_ss.add(when: 'CONFIG_USB_XHCI', if_true: files('hcd-xhci.c'))
system_ss.add(when: 'CONFIG_USB_XHCI_PCI', if_true: files('hcd-xhci-pci.c'))
system_ss.add(when: 'CONFIG_USB_XHCI_SYSBUS', if_true: files('hcd-xhci-sysbus.c'))

3
include/hw/i386/pc.h
View File

@ -31,7 +31,7 @@ typedef struct PCMachineState {
Notifier machine_done;
/* Pointers to devices and objects: */
PCIBus *bus;
PCIBus *pcibus;
I2CBus *smbus;
PFlashCFI01 *flash[2];
ISADevice *pcspk;
@ -92,7 +92,6 @@ struct PCMachineClass {
/* Device configuration: */
bool pci_enabled;
bool kvmclock_enabled;
const char *default_south_bridge;
/* Compat options: */

2
include/hw/i386/x86.h
View File

@ -139,7 +139,7 @@ typedef struct GSIState {
qemu_irq x86_allocate_cpu_irq(void);
void gsi_handler(void *opaque, int n, int level);
void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
void ioapic_init_gsi(GSIState *gsi_state, Object *parent);
DeviceState *ioapic_init_secondary(GSIState *gsi_state);
/* pc_sysfw.c */

2
include/hw/misc/macio/macio.h
View File

@ -28,7 +28,7 @@
#include "hw/char/escc.h"
#include "hw/pci/pci_device.h"
#include "hw/ide/internal.h"
#include "hw/ide/ide-bus.h"
#include "hw/intc/heathrow_pic.h"
#include "hw/misc/macio/cuda.h"
#include "hw/misc/macio/gpio.h"

36
include/hw/nubus/nubus-virtio-mmio.h Normal file
View File

@ -0,0 +1,36 @@
/*
* QEMU Macintosh Nubus Virtio MMIO card
*
* Copyright (c) 2023 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_NUBUS_VIRTIO_MMIO_H
#define HW_NUBUS_VIRTIO_MMIO_H
#include "hw/nubus/nubus.h"
#include "qom/object.h"
#include "hw/intc/goldfish_pic.h"
#include "hw/virtio/virtio-mmio.h"
#define TYPE_NUBUS_VIRTIO_MMIO "nubus-virtio-mmio"
OBJECT_DECLARE_TYPE(NubusVirtioMMIO, NubusVirtioMMIODeviceClass,
NUBUS_VIRTIO_MMIO)
struct NubusVirtioMMIODeviceClass {
DeviceClass parent_class;
DeviceRealize parent_realize;
};
#define NUBUS_VIRTIO_MMIO_NUM_DEVICES 32
struct NubusVirtioMMIO {
NubusDevice parent_obj;
GoldfishPICState pic;
VirtIOMMIOProxy virtio_mmio[NUBUS_VIRTIO_MMIO_NUM_DEVICES];
};
#endif

2
include/hw/nubus/nubus.h
View File

@ -51,7 +51,7 @@ struct NubusBus {
qemu_irq irqs[NUBUS_IRQS];
};
#define NUBUS_DECL_ROM_MAX_SIZE (128 * KiB)
#define NUBUS_DECL_ROM_MAX_SIZE (1 * MiB)
struct NubusDevice {
DeviceState qdev;

1
include/hw/sysbus.h
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@ -83,7 +83,6 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr);
void sysbus_mmio_map_overlap(SysBusDevice *dev, int n, hwaddr addr,
int priority);
void sysbus_mmio_unmap(SysBusDevice *dev, int n);
MemoryRegion *sysbus_address_space(SysBusDevice *dev);
bool sysbus_realize(SysBusDevice *dev, Error **errp);
bool sysbus_realize_and_unref(SysBusDevice *dev, Error **errp);

1
include/hw/usb.h
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@ -498,7 +498,6 @@ struct USBBusOps {
void usb_bus_new(USBBus *bus, size_t bus_size,
USBBusOps *ops, DeviceState *host);
void usb_bus_release(USBBus *bus);
USBBus *usb_bus_find(int busnr);
void usb_legacy_register(const char *typename, const char *usbdevice_name,
USBDevice *(*usbdevice_init)(void));
USBDevice *usbdevice_create(const char *cmdline);

13
include/qom/object.h
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@ -1550,6 +1550,19 @@ Object *object_resolve_path(const char *path, bool *ambiguous);
Object *object_resolve_path_type(const char *path, const char *typename,
bool *ambiguous);
/**
* object_resolve_type_unambiguous:
* @typename: the type to look for
* @errp: pointer to error object
*
* Return the only object in the QOM tree of type @typename.
* If no match or more than one match is found, an error is
* returned.
*
* Returns: The matched object or NULL on path lookup failure.
*/
Object *object_resolve_type_unambiguous(const char *typename, Error **errp);
/**
* object_resolve_path_at:
* @parent: the object in which to resolve the path

16
qom/object.c
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@ -2229,6 +2229,22 @@ Object *object_resolve_path_at(Object *parent, const char *path)
return object_resolve_abs_path(parent, parts, TYPE_OBJECT);
}
Object *object_resolve_type_unambiguous(const char *typename, Error **errp)
{
bool ambig;
Object *o = object_resolve_path_type("", typename, &ambig);
if (ambig) {
error_setg(errp, "More than one object of type %s", typename);
return NULL;
}
if (!o) {
error_setg(errp, "No object found of type %s", typename);
return NULL;
}
return o;
}
typedef struct StringProperty
{
char *(*get)(Object *, Error **);