riscv: spike: Remove target macro conditionals
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
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@ -317,7 +317,7 @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
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mc->init = spike_board_init;
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mc->init = spike_board_init;
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mc->max_cpus = SPIKE_CPUS_MAX;
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mc->max_cpus = SPIKE_CPUS_MAX;
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mc->is_default = true;
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mc->is_default = true;
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mc->default_cpu_type = SPIKE_V1_10_0_CPU;
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mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
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mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
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mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
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mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
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mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
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mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
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mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
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@ -47,10 +47,4 @@ enum {
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SPIKE_DRAM
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SPIKE_DRAM
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};
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};
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#if defined(TARGET_RISCV32)
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
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#elif defined(TARGET_RISCV64)
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
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#endif
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#endif
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#endif
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