From 8d031cec366f26669807eb43f61eb335973b7053 Mon Sep 17 00:00:00 2001 From: Pu Wen Date: Tue, 16 Apr 2019 20:06:13 +0800 Subject: [PATCH 1/4] i386: Add new Hygon 'Dhyana' CPU model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new base CPU model called 'Dhyana' to model processors from Hygon Dhyana(family 18h), which derived from AMD EPYC(family 17h). The following features bits have been removed compare to AMD EPYC: aes, pclmulqdq, sha_ni The Hygon Dhyana support to KVM in Linux is already accepted upstream[1]. So add Hygon Dhyana support to Qemu is necessary to create Hygon's own CPU model. Reference: [1] https://git.kernel.org/tip/fec98069fb72fb656304a3e52265e0c2fc9adf87 Signed-off-by: Pu Wen Message-Id: <1555416373-28690-1-git-send-email-puwen@hygon.cn> Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 2 ++ 2 files changed, 52 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e1687f7547..d92b0f6fcc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2935,6 +2935,56 @@ static X86CPUDefinition builtin_x86_defs[] = { .model_id = "AMD EPYC Processor (with IBPB)", .cache_info = &epyc_cache_info, }, + { + .name = "Dhyana", + .level = 0xd, + .vendor = CPUID_VENDOR_HYGON, + .family = 24, + .model = 0, + .stepping = 1, + .features[FEAT_1_EDX] = + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | + CPUID_VME | CPUID_FP87, + .features[FEAT_1_ECX] = + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | + CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | + CPUID_EXT_MONITOR | CPUID_EXT_SSE3, + .features[FEAT_8000_0001_EDX] = + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] = + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | + CPUID_EXT3_TOPOEXT, + .features[FEAT_8000_0008_EBX] = + CPUID_8000_0008_EBX_IBPB, + .features[FEAT_7_0_EBX] = + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | + CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, + /* + * Missing: XSAVES (not supported by some Linux versions, + * including v4.1 to v4.12). + * KVM doesn't yet expose any XSAVES state save component. + */ + .features[FEAT_XSAVE] = + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, + .features[FEAT_SVM] = + CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, + .xlevel = 0x8000001E, + .model_id = "Hygon Dhyana Processor", + .cache_info = &epyc_cache_info, + }, }; typedef struct PropValue { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 828067bd1c..0128910661 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -726,6 +726,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_VENDOR_VIA "CentaurHauls" +#define CPUID_VENDOR_HYGON "HygonGenuine" + #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ From 965242dbf47192a96472290302a66a4bd620f368 Mon Sep 17 00:00:00 2001 From: Ernest Esene Date: Wed, 27 Mar 2019 17:53:56 +0100 Subject: [PATCH 2/4] Categorize devices: IGD passthrough ISA bridge Set category for the device. Signed-off-by: Ernest Esene Message-Id: <20190327133714.GA9329@erokenlabserver> Reviewed-by: Eduardo Habkost [ehabkost: edited commit message] Signed-off-by: Eduardo Habkost --- hw/i386/pc_piix.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 8ad8e885c6..03a9cb8af3 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -911,6 +911,7 @@ static void isa_bridge_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); dc->desc = "ISA bridge faked to support IGD PT"; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); k->vendor_id = PCI_VENDOR_ID_INTEL; k->class_id = PCI_CLASS_BRIDGE_ISA; }; From 1ec202c9bed532ea629af9ce95485dd36a183250 Mon Sep 17 00:00:00 2001 From: Ernest Esene Date: Wed, 27 Mar 2019 18:05:18 +0100 Subject: [PATCH 3/4] Categorize devices: iommu Set category and description for iommu devices. Signed-off-by: Ernest Esene Message-Id: <20190327170518.GA16887@erokenlabserver> Reviewed-by: Eduardo Habkost [ehabkost: edited commit message] Signed-off-by: Eduardo Habkost --- hw/i386/amd_iommu.c | 2 ++ hw/i386/intel_iommu.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 6eabdf9917..4a4e2c7fd4 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1601,6 +1601,8 @@ static void amdvi_class_init(ObjectClass *klass, void* data) dc_class->int_remap = amdvi_int_remap; /* Supported by the pc-q35-* machine types */ dc->user_creatable = true; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->desc = "AMD IOMMU (AMD-Vi) DMA Remapping device"; } static const TypeInfo amdvi = { diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2558f48fe6..44b1231157 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3741,6 +3741,8 @@ static void vtd_class_init(ObjectClass *klass, void *data) x86_class->int_remap = vtd_int_remap; /* Supported by the pc-q35-* machine types */ dc->user_creatable = true; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->desc = "Intel IOMMU (VT-d) DMA Remapping device"; } static const TypeInfo vtd_info = { From a4e0b436f44a4bb47ed4a75b0c05d2547cf12b1c Mon Sep 17 00:00:00 2001 From: Stanislav Lanci Date: Tue, 16 Apr 2019 14:38:33 +0200 Subject: [PATCH 4/4] Pass through cache information for TOPOEXT CPUs Signed-off-by: Stanislav Lanci Message-Id: <20190416123833.60649-1-pixo@polepetko.eu> [ehabkost: removed redundant comment line] Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d92b0f6fcc..722c5514d4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4591,6 +4591,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 0x8000001D: *eax = 0; + if (cpu->cache_info_passthrough) { + host_cpuid(index, count, eax, ebx, ecx, edx); + break; + } switch (count) { case 0: /* L1 dcache info */ encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,