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target/sparc: Implement FPMIN, FPMAX

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-11-04 21:39:59 -07:00
parent b3c934dd34
commit db11dfea83
2 changed files with 28 additions and 0 deletions
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14
target/sparc/insns.decode
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@ -524,6 +524,20 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
FPSUBUS8 10 ..... 110110 ..... 1 0101 0111 ..... @d_d_d
FPSUBUS16 10 ..... 110110 ..... 1 0101 0011 ..... @d_d_d
FPMIN8 10 ..... 110110 ..... 1 0001 1010 ..... @d_d_d
FPMIN16 10 ..... 110110 ..... 1 0001 1011 ..... @d_d_d
FPMIN32 10 ..... 110110 ..... 1 0001 1100 ..... @d_d_d
FPMINU8 10 ..... 110110 ..... 1 0101 1010 ..... @d_d_d
FPMINU16 10 ..... 110110 ..... 1 0101 1011 ..... @d_d_d
FPMINU32 10 ..... 110110 ..... 1 0101 1100 ..... @d_d_d
FPMAX8 10 ..... 110110 ..... 1 0001 1101 ..... @d_d_d
FPMAX16 10 ..... 110110 ..... 1 0001 1110 ..... @d_d_d
FPMAX32 10 ..... 110110 ..... 1 0001 1111 ..... @d_d_d
FPMAXU8 10 ..... 110110 ..... 1 0101 1101 ..... @d_d_d
FPMAXU16 10 ..... 110110 ..... 1 0101 1110 ..... @d_d_d
FPMAXU32 10 ..... 110110 ..... 1 0101 1111 ..... @d_d_d
FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5
FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \
rs1=%dfp_rs1 rs2=%dfp_rs2

14
target/sparc/translate.c
View File

@ -5061,6 +5061,20 @@ TRANS(FSRL32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_shrv)
TRANS(FSRA16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sarv)
TRANS(FSRA32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sarv)
TRANS(FPMIN8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_smin)
TRANS(FPMIN16, VIS4, do_gvec_ddd, a, MO_16, tcg_gen_gvec_smin)
TRANS(FPMIN32, VIS4, do_gvec_ddd, a, MO_32, tcg_gen_gvec_smin)
TRANS(FPMINU8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_umin)
TRANS(FPMINU16, VIS4, do_gvec_ddd, a, MO_16, tcg_gen_gvec_umin)
TRANS(FPMINU32, VIS4, do_gvec_ddd, a, MO_32, tcg_gen_gvec_umin)
TRANS(FPMAX8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_smax)
TRANS(FPMAX16, VIS4, do_gvec_ddd, a, MO_16, tcg_gen_gvec_smax)
TRANS(FPMAX32, VIS4, do_gvec_ddd, a, MO_32, tcg_gen_gvec_smax)
TRANS(FPMAXU8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_umax)
TRANS(FPMAXU16, VIS4, do_gvec_ddd, a, MO_16, tcg_gen_gvec_umax)
TRANS(FPMAXU32, VIS4, do_gvec_ddd, a, MO_32, tcg_gen_gvec_umax)
static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_i64, TCGv_i64))
{