tcg/aarch64: Reserve TCG_REG_TMP1, TCG_REG_TMP2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -40,11 +40,12 @@ static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
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TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
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TCG_REG_X16, TCG_REG_X17,
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TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
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TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
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/* X16 reserved as temporary */
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/* X17 reserved as temporary */
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/* X18 reserved by system */
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/* X19 reserved for AREG0 */
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/* X29 reserved as fp */
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@ -71,7 +72,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
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return TCG_REG_X0 + slot;
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}
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#define TCG_REG_TMP0 TCG_REG_X30
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#define TCG_REG_TMP0 TCG_REG_X16
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#define TCG_REG_TMP1 TCG_REG_X17
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#define TCG_REG_TMP2 TCG_REG_X30
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#define TCG_VEC_TMP0 TCG_REG_V31
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#ifndef CONFIG_SOFTMMU
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@ -2902,6 +2905,8 @@ static void tcg_target_init(TCGContext *s)
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
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tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0);
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}
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