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target/arm: Enable SCR and HCR bits for RAS

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Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-05-06 13:02:32 -05:00 committed by Peter Maydell
parent 58e93b48aa
commit da3d8b1362
1 changed files with 9 additions and 0 deletions
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9
target/arm/helper.c
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@ -1755,6 +1755,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
}
valid_mask &= ~SCR_NET;
if (cpu_isar_feature(aa64_ras, cpu)) {
valid_mask |= SCR_TERR;
}
if (cpu_isar_feature(aa64_lor, cpu)) {
valid_mask |= SCR_TLOR;
}
@ -1769,6 +1772,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
}
} else {
valid_mask &= ~(SCR_RW | SCR_ST);
if (cpu_isar_feature(aa32_ras, cpu)) {
valid_mask |= SCR_TERR;
}
}
if (!arm_feature(env, ARM_FEATURE_EL2)) {
@ -5126,6 +5132,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
if (cpu_isar_feature(aa64_vh, cpu)) {
valid_mask |= HCR_E2H;
}
if (cpu_isar_feature(aa64_ras, cpu)) {
valid_mask |= HCR_TERR | HCR_TEA;
}
if (cpu_isar_feature(aa64_lor, cpu)) {
valid_mask |= HCR_TLOR;
}